- 學位論文
高電壓電荷幫浦之設計與分析
High Voltage Charge Pump Circuits of Design and Analysis
摘要
在本論文中，我們討論四個新設計的電荷幫浦電路。在這些電路中，共同的特點就是皆使用倍壓脈波產生器。在第一個電路中，藉由串接多級倍壓脈波產生器，使其構成電荷幫浦電路，我們稱此電路為VDCP-1。第二個電路是VDCP-1的改良，其特點乃是在輸出端之峰值檢波電路中，將NMOS電晶體，改成互補式並聯的PMOS電晶體，此電路我們稱之為VDCP-2。第三、四個電路(MVDCP-1、MVDCP-2)是利用倍壓脈波產生器的輸出，提供給狄克森電荷幫浦電路之時脈電壓，而MVDCP-1、MVDCP-2之差別僅在於電路接法稍有不同。以上四種電路均藉由HSpice 0.35μm TSMC之製程模擬，其結果均顯示出比文獻上的升壓電路有更佳之昇壓效果。 其中VDCP-1亦藉由TSMC 0.35μm Mixed-Signal 製程來實現IC晶片，此晶片大小為1.0404 × 1 (mm2)，其電路消耗功率為5.84mW。
關鍵字
電荷幫浦並列摘要
There are four new charge pump circuits were presented in thesis. These four new circuits were base on the voltage-doubler clock generator. The first one was constituted by connecting many stages of voltage-doubler clock generator and which was called VDCP-1. The second charge pump circuit, VDCP-2, was a modification of VDCP-1. A complement-paralleled pMOSFET was used to replace the nMOSFET of the output. For the other two charge pump circuits, the multi-stages voltage doubler was used to be clock generator, which providing clock voltage to transfer MOS diode. The two circuits showed little difference in connection with each other, and call MVDCP-1 and MVDCP-2, respectively. The above four circuits were simulated by HSpice in TSMC 0.35μm process. They all showed batter results than conventional charge pump circuit. The Layout design of VDCP-1 was also realized through TSMC 0.35μm Mixed-Signal process. In the chip, the area is 1.0404 × 1 (mm2) and the power consumption of the circuit is 5.84mW.