以主動負載差動放大器為基礎的壓控振盪器與鎖相迴路之研究

A Study of VCO & PLL Based on Active Load Differential Amplifiers

張家祥(Chia-Hsiang Chang)

指導教授 ： 蔡澈雄

崑山科技大學/工程學院/電子工程研究所/碩士(2010年)

https://doi.org/10.6828/KSU.2010.00056

摘要

本論文中利用差動式的高輸入阻抗、高輸出阻抗和高電壓增益來實現壓控振盪器( VCO )電路並將運用在鎖相迴路( PLL )系統電路中。其中差動放大壓控振盪器電路是以差動放大器為設計基礎架構，設計出 CMOS 與 BiCMOS 兩種差動放大壓控振盪器。於鎖相迴路方面，是以主動負載差動振盪器為主要核心，來設計 CMOS 主動負載振盪器的鎖相迴路。
使用Advanced Design System (ADS)來進行電路模擬與驗證，差動放大器組成的壓控振盪器的製程為 tsmc 0.35-μm BiCMOS，而主動負載鎖相迴路的製程為tsmc 0.18-μm CMOS。
主要效能為：壓控振盪器有寬頻率調變範圍，控制電壓由0.7 V到1.8 V，振盪頻率從399 MHz到4134 MHz，PLL鎖定頻率為2880 MHz，鎖定時間小於4 μs，輸出功率為10.707 dBm，消耗功率為 7.398 mW，PLL的迴路濾波器是包含在晶片中，晶片面積為623×623 μm2。

關鍵字

主動負載差動放大器 ； 壓控振盪器 ； 鎖相迴路

並列摘要

In this thesis, we use the differential amplifier with high input impedance, high output impedance and high voltage gain characteristics, to implement a differential amplifier voltage controlled oscillator ( VCO ),and can be applied on PLL circuit design. The differential amplifier voltage controlled oscillator ( VCO ) base on the framework of differential amplifier, to design CMOS and BiCMOS differential amplifier voltage controlled oscillators. In the Phase-Locked Loop ( PLL ) circuit takes active load differential amplifier oscillator as main core to design CMOS active load differential amplifier oscillator.
This circuit is simulated and verified by Advanced Design System (ADS), with tsmc 0.35-μm BiCMOS technology for the differential amplifier Ring VCO, and tsmc 0.18-μm CMOS technology for the active load PLL.
Key performance：the VCO has a wide operating frequency range, from 399 MHz to 4134 MHz with 0.7 V to 1.8 V supply voltage, The PLL lock frequency is 2880 MHz, and lock time is under 4 μs, and total power consumption is 7.398 mW and the output power is 10.707 dBm. The complete PLL including its on-chip loop filter occupies 623×623 μm2.

並列關鍵字

Active Load Differential Amplifier ； VCO ； PLL

參考文獻

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