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  • 學位論文

在工作模式下中央處理器省能方式之研究

Study of CPU Energy Saving on the Working Mode

指導教授 : 謝聰烈
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摘要


本論文是以雙相直流降壓調變器為基礎,討論筆記型處理器由高耗電的工作模式變為低耗電的工作模式時,這時候雙相的調變系統效率會變極差,為改善此點,筆記型處理器的廠商提出以減少電壓調節模組控制相數做為其解決方案,此法稱為“電源狀態標示”。將電源狀態標示啟動時,電壓調節模組會由雙相控制系統變成單相系統,而其效能會因電源狀態標示的開啟而提高。之前開啟的時間點並未強制規定或要求。現在因節能省碳的要求,故改變啟動的方式。近年處理器因為串列訊號的發展,已由只能發電壓位準的串列電壓識別變成並列電壓識別,此種改變,中央處理器就可以發出開啟電源狀態標示的要求。因為電源狀態標示是以雙相調變控制器做為基礎,所以將介紹如何設計一個高效能的雙相調變控制器,並提出如何找出合適的元件,在高效率的雙相調變控制器下,找出單相與雙相效率的交會點,如此可以得到電源狀態標示開啟的點。利用此交會點再加上軟體的設定與處理器本身電流的要求,即可得到安全與高效率的電源狀態標示控制點。

並列摘要


This thesis is based on dual Phase step-down DC modulator to discuss how to improve the Voltage Regulator Module efficiency of CPU. When the CPU is in heavy loading, the dual phase Voltage Regulator Module efficiency is excellent. The loading change to light the Voltage Regulator Module efficiency is very poor. For this problem, the CPU vendor would provide a solution for this issue. The solution is “Power State Indicate”. The Power State Indicate is base on dual phase step-down DC modulator. When CPU is in light loading, the CPU will enable Power State Indicate. The Voltage Regulator Module would follow command to disable one phase. The power source would from dual phase change to single phase. The efficiency of Voltage Regulator Module will be increased. The power consumption will be decreased. The battery life will improve. This improve is very important for power design. We must find out the Power State Indicate enable “POINT”. This thesis will discuss design a high efficiency Voltage Regulator Module and how to enable Power State Indicate point.

並列關鍵字

PSI Buck VRM CPU

參考文獻


[1] Intel, “VR12/IMVP7 Pulse Width Modulation (PWM) Specification,” Ver. 1.5, 2010.
[4] 游宗達,“四相式DC/DC降壓電源轉換器之分析與設計”,碩士論文, 大同大學,2008。
[7] Intel etal, “Advanced Configuration and Power Interface Specification,” Rev. 4.0a, 2010.
[13] 游明輝,“太陽能輔助電動輪椅系統架構之研製”,碩士論文,崑山科技大學,2010。
[16] IDT, “IDTP62000 Datebook,” Rev. E, 2010.

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