1.8伏特十位元連續逼近式類比數位轉換器設計與製作

The Design and Implementation of 1.8V 10-bits Successive Approximation Register Analog-to-Digital Converter

黃頂科(Ding-Ke Huang)

指導教授 ： 呂啟彰

國立虎尾科技大學/電機資訊學院/電機工程研究所/碩士(2014年)

https://doi.org/10.6827/NFU.2014.00114

摘要

由於現今訊號大都需要將類比訊號轉換成數位訊號來進行處理，因此在混合訊號的設計電路，類比數位轉換器便是個極為重要的部分。在各種類比數位轉換器電路中，連續逼近式架構具有低功率消耗及優良的轉換精確度，本論文以連續逼近式架構進行設計，整體電路包含取樣與保持電路、比較器、數位類比轉換電路、時脈產生器和逐漸逼近暫存器；在取樣保持電路上使用拔靴帶式開關以改善導通電阻及線性度問題；在數位類比轉換電路上，則結合傳統二進制加權電容陣列與C-2C電容陣列以及雙取樣的技術，其中高位元部份使用傳統二進制加權電容陣列，低位元部份則使用C-2C電容陣列，以降低整體電容值，達到降低面積及功率消耗的目的。
本論文中，使用TSMC 0.18μm 1P6M的製程，實現一個電源電壓為1.8伏特，取樣頻率為727kHz的十位元連續逼近式類比數位轉換器。當輸入訊號為13.5KHz時，經由佈局後模擬可得到SFDR與SNDR分別為38.73dB 與37.69dB、有效位元數為5.96位元、差值非線性介於-0.71~0.96 LSB之間、積分非線性介於-1.22~1.49 LSB之間、功率消耗約為150.83μW，佈局後核心晶片面積為0.217135×0.26828mm2 ，此電路架構模擬結果與傳統架構結果相比較，改善整體晶片面積以及功率消耗，驗證了此技術的優點。

關鍵字

連續逼近式 ； 類比數位轉換器

並列摘要

Typical signal processing need to convert analog signals into digital signals for analysis, so the design analog-to-digital converter is an extremely important part of the mixed-signal system. In this paper, use successive approximation register architecture to design circuits for excellent balance between the power consumption and conversion accuracy. The entire circuit consists of sample-and-hold circuit, comparator, digital-to-analog converter, clock generator, and successive approximation register. Sample-and-hold circuit using bootstraped switch to improve on-resistance and linearity. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC.
In this research, 10-bits 727kS/s SAR ADC under a single 1.8V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 38.73dB and SNDR of
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37.69dB. The peak DNL is -0.71LSB ~ 0.96 LSB, the peak INL is -1.22LSB ~ 1.49LSB, and the power dissipation is about 150.83μW, the layout area is 0.217135×0.26828mm2. The circuit architecture simulation results are compared with the conventional architecture, to verify the practicality and advantages of this technology, especially to reduce the overall chip area and power consumption.

並列關鍵字

Successive Approximation ； Analog-to-Digital Converter

參考文獻

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