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  • 學位論文

具即時電流補償之快速暫態線性穩壓器的設計與實現

The Design and Implementation of Fast-Transient Low-Dropout Regulator with Real-Time Current Compensation Circuit

指導教授 : 陳厚銘
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摘要


在傳統的線性穩壓器中,由於線性穩壓器的特性會隨著負載不同而有所變化,為了確保不同負載下的穩定度,頻寬必定會遭受到限制,導致暫態方面的特性隨之受限。因此我們期望能克服傳統架構上會遇到的瓶頸,使得穩壓器能實現好的暫態響應。 本篇論文提出具即時電流補償的快速暫態線性穩壓器,即時電流補償電路包含了一個磁滯比較器和兩個能夠觸發PMOS和NMOS的控制器。當比較器偵測到輸出端電壓的變化時,比較器將產生邏輯訊號給控制器,再藉由控制器來觸發P型或N型電晶體進一步影響功率電晶體的閘極電位。快速暫態的線性穩壓器通常運用在可攜式產品或無線射頻上,像是手機、筆記型電腦、PDA等。 具即時電流補償電路之快速暫態線性穩壓器是使用台積電0.35μm CMOS製程,面積為1030.4 x 1026.2μm2,其工作電壓操作於2.7~3.3V,輸出電壓為1V,且最大能提供50mA的負載電流變化。由模擬結果顯示出,從輕載切換至重載時改善了68mV的輸出電壓變化和41%的穩定時間,從重載切換至輕載時改善了60mV的輸出電壓變化和78%的穩定時間。

並列摘要


In the traditional linear regulator, due to the characteristics of the linear regulator will vary with load, in order to ensure stability under different load, the bandwidth will be subjected to restrictions, leading to transient aspects of along with limited features. Therefore, we expect to encounter on the traditional architecture can overcome the bottleneck, so the regulator can achieve good transient response. A fast-transient linear regulator with real-time current compensation circuit was proposed. The real-time current compensation circuit contains a hysteresis comparator and two controllers which can trigger off PMOS and NMOS. While the comparator sensed the variation of output voltage, it will send a logical signal to controllers then affect the power mosfet of gate voltage by P-type or N-type transistors. Fast-transient linear regulator usually used in portable products or RFID, such as mobile phone, note book, PDA, etc. The proposed fast-transient low-dropout regulator with real-time current compensation circuit was fabricated in TSMC 0.35μm CMOS technology and active area was 253.5 x 113.7μm2 and The LDO operates range from 2.7V to 3.3V and the regulated voltage is 1V that provide 50mA maximum load current variation. Simulation results shows that the proposed circuit improved 68mV output voltage variation and 41% stable time from light load to heavy load, 60mV output voltage variation and 78% stable time from heavy to light load.

參考文獻


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[5] M. Horowitz, T. Indermaur and R. Gonzafez, “Low-power digital design” IEEE Symposium on Low Power Electronics, pp. 8-11, 1994.
[6] Ka Nang Leung, “A CMOS Low-Dropout Regulator with a Momentarily Current-Boosting Voltage Buffer” IEEE Transactions on Circuit and Systems, VOL.57, NO9, September 2010.
[7] Jia-Hui Wang, Chun-Hung Yang, Chien-Hung Tsai “A Fast-Transient Low-Dropout Regulator with Current-Feedback-Buffer(CFB) for SoC Application” IEEE Next-Generation Electronics, 2010.

被引用紀錄


鍾佳哲(2015)。低壓差線性穩壓器的設計與實現〔碩士論文,國立虎尾科技大學〕。華藝線上圖書館。https://www.airitilibrary.com/Article/Detail?DocID=U0028-2008201513053100

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