應用於影像視訊編解碼離散餘弦轉換架構之非精確加法器設計

本文提出應用於視訊編解碼器離散餘弦轉換(Discrete Cosine Transform；DCT)之進位相關加法器(Carry Correlative Adder；CCA)，以全加器(Full Adder；FA)為基礎，設計非精確全加器(Imprecise FA；IFA)。將CCA應用於漣波進位加法器(Ripple Carry Adder；RCA)成為非精確漣波進位加法器(Imprecise RCA；IRCA)，在高位元部分使用FA，而低位元部分則是使用IFA，並將此IRCA應用於8x8 2D-DCT/2D-IDCT架構。輸入原始影像做2D-DCT與2D-IDCT處理後，計算峰值訊雜比(Peak signal-to-noise ratio；PSNR)。在低位元部分使用4位元CCA的模擬結果為PSNR=39.49dB，比鏡像近似加法器(Mirror Approximation Adder；MAA)與簡化全加器(Simplified Full Adder；SFA)在低位元部分使用4位元IFA的模擬結果還要高。由於CCA的進位不會傳遞，所以關鍵路徑不會因為位元寬度的增加而增加，故CCA的延遲可以被減少。CCA的延遲與SFA及每個MAA相近，成本比精確加法器低。雖然CCA的成本比MAA1及MAA2高，但CCA的PSNR最高，而CCA平均消耗功率約為FA平均消耗功率的63%。

關鍵字

非精確加法器；進位相關加法器

並列摘要

An imprecise full adder called Carry Correlative Adder (CCA) for Discrete Cosine Transform (DCT) of image/video codec is proposed in this thesis. The Imprecise Full Adder (IFA) is designed based on Full Adder (FA). The imprecise adder called CCA is constructed by applying CCA to lower bits, and applying full adder to higher bits of Ripple Carry Adder (RCA). Then apply the imprecise adder to 8x8 2D-DCT/2D-IDCT architecture. Peak Signal-to-Noise Ratio (PSNR) is calculated after input the original image to the 2D-DCT and 2D-IDCT architectures sequentially. As CCA is utilized in the lower 4 bits of RCA, PSNR is 39.49dB which is higher than PSNR when all the Mirror Approximation Adders (MAA) or Simplified Full Adder (SFA) is utilized. The critical path of the CCA adder won’t be increased with increasing the word-length, because the carry won’t be propagated. Hence, the delay of CCA adder can be reduced. In addition, the delay of CCA is very close to that of SFA and every MAA. The cost of CCA adder applied is lower than precise adder. Although the cost of CCA is higher than MAA1 and MAA2, the PSNR of CCA is also the highest. The average power consumption of CCA is 63% average power consumption of FA.

並列關鍵字

Imprecise Adder ； Carry Correlation Adder

參考文獻

[2]Doochul Shin, Sandeep K. Gupta, “A Re-Design Technique for Datapath Modules in Error Tolerant Application,” 17th Asian Test Symposium (ATS ’08), pp. 431-437, Nov. 2008.

[6]S. Lee and K. Cho, “Architecture of transform circuit for video decoder supporting multiple standards,” Electron. Lett., vol. 44, pp. 274-275, Feb. 2008.

[7]Yeong-Kang Lai, Yu-Fan Lai, “A Reconfigurable IDCT Processor Architecture for Video Coding,” ICMES., pp.469-472, 2009.

[8]S. Lee and K. Cho, “Design of transform and quantization circuit for multi-standard integrated video decoder,” in Proc. IEEE Workshop Signal Processing Systems, pp. 181-186, Oct. 2007.

[9]S. Lee and K. Cho, “Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder,” in Proc. Int. Conf. Design and Technology of Integrated Systems in Nanoscale Era, pp. 102-107, Sep. 2007.

國際替代計量

應用於影像視訊編解碼離散餘弦轉換架構之非精確加法器設計

未授權

主題瀏覽