高鍺組成之矽鍺合金材料以低壓氧化成長介電層與其選擇性氧化機制之研究

A Study of High-Ge-Content Si0.16Ge0.84 Gate Stack and Selective Oxidation Mechanism by Low Pressure Oxidation

張濬麟(Jun-Lin Zhang)

指導教授 ： 簡昭欣

國立交通大學/電機學院/電子工程系所/碩士(2018年)

摘要

半導體產業在過去數十年之中有著爆炸性的成長，這當中的關鍵在於電晶體尺寸的微縮使得晶片效能的提升，然而尺寸的微縮漸漸面臨了物理極限的瓶頸，因此我們開始尋找新的材料來取代目前以矽基板為材料的元件，在這當中高鍺組成之矽鍺材料因為有較高載子遷移率以及能利用磊晶技術整合於當前矽基板製程上而被視為未來世代相當具有潛力的材料，因此本篇論文主要針對高鍺組成之矽鍺材料進行深入的研究。本論文研究中，我們探討了以低壓氧化技術應用在高鍺組成之矽鍺材料上的元件製備可行性，這當中包含低壓氧化過程之原子移動行為以及低壓氧化製作閘極介電層之電特性進行深入研究。
第一部分，我們利用低壓化學氣相沉積(LPCVD)系統將單晶矽鍺磊晶於矽基板上，並利用一連串材料分析來驗證薄膜組成比例(Si0.16Ge0.84)與薄膜應力百分比(66%)。接著我們利用不同低壓氧化時間來成長氧化層，根據材料分析的結果，我們建構了一個在低壓氧化過程中原子移動的氧化模型。在低壓氧化過程中，因為選擇性氧化矽原子而產生了鍺原子的聚積層，此時矽原子會因為濃度差異而有一個往表面擴散的行為，隨著氧化時間提高，鍺聚積層厚度大於矽原子擴散長度，而生成了混合的氧化層(Si-O+Ge-O)。為了避免混合氧化層生成以及鍺聚積的行為，我們在後續製作電容時將氧化時間設定為5分鐘。
第二部分，我們以低壓氧化技術製作電容並探討其電特性，我們發現隨著氧化溫度提升以及氧氣壓力下降，電容的電特性有顯著的改善，在氧化溫度600 C/氧氣壓力0.01 torr條件下有最好的電特性，分別為等效氧化層厚度(EOT) 1.5nm，最小的閘極漏電流密度(JG) 5.8×10-7 A/cm2，以及最小的頻率分散(FD) 1.4%。我們也利用了不同方法萃取出介面能態密度(Dit)，在氧化溫度600 C/氧氣壓力0.01 torr條件下有最小的值2.0×1012 cm-2eV-1。
最後一部分，我們利用材料分析方法萃取了介面氧化層的組成比例，我們發現隨著氧氣壓力下降，可以有效抑制鍺的氧化行為；而當氧化溫度提高，可以看到矽的氧化態傾向更完整的鍵結。在氧化溫度600 C/氧氣壓力0.01 torr條件下有最高的氧化矽比例80%，以及最低的氧化鍺比例20%。最終，我們可以將電特性的改善歸因於減少氧化鍺的比例。

關鍵字

矽鍺材料磊晶 ； 矽鍺低壓氧化模型 ； 矽鍺電容

並列摘要

In this thesis, we have comprehensively investigated the feasibility in using low pressure oxidation (LPO) process on high-Ge-content (HGC) SiGe for next generation CMOS devices technology, including oxidation behavior, gate stacks, and electrical characteristics extraction.
Firstly, in order to integrate HGC SiGe on Si platform, we investigated hetero-epitaxial HGC SiGe on blanket Si substrate accompanied with Ge buffer layer. A series of material analyses affirmed the HGC Si0.16Ge0.84 composition and strain percentage (66%). To realize the oxide layer formation during LPO process, we examined the oxide composition with various LPO process time. Based on the results, we proposed the speculated oxidation model to explain the Si, Ge, and O atoms diffusion during LPO process.
Next, we employed LPO process to achieve a high quality dielectric gate stack on HGC Si0.16Ge0.84 substrate. The LPO process possessed a Si-cap free passivation method, and exhibited the superior electrical characteristics with moderate equivalent oxide thickness (EOT) ~1.5 nm and low gate leakage current density (JG) 5.8×10-7 A/cm2 while it greatly reduced the frequency dispersion (FD) of Cacc to 1.4%. Moreover, to extract the accurate interface trap density (Dit) value, the conductance method and two-band admittance circuit model were implemented. The extracted results showed that the Dit value was reduced to 2.0×1012 cm-2eV-1 with LPO condition of 600 C/ 0.01 torr.
In the end, we comprehensively studied the interfacial layer (IL) formation and composition by X-ray photoelectron spectroscopy (XPS) analysis. The results revealed that a highest SiOx composition (~80%) with a lowest GeOx composition (~20%) in the IL was controllable by using LPO process. This result evidenced that the LPO process was a promising method to selectively oxidize Si atoms without GeOx formation. Furthermore, we have also presented the relevance between GeOx percentage in the IL and electrical characteristics. The results showed that the suppression of GeOx formation was attributed to the superior interface quality. In conclusion, on the basis of abovementioned results of experiments, we could expect that the LPO process was a promising approach for next generation HGC SiGe channel MOSFETs.

並列關鍵字

SiGe epitaxial technology ； SiGe low-pressure-oxidation model ； SiGe MOSCAPs

參考文獻

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