低功耗與低成本之二維對稱式濾波器架構設計實現

Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures

陳姵妤(Pei-Yu Chen)

指導教授 ： 范倫達 ； Hari C. Reddy

國立交通大學/資訊學院/資訊科學與工程研究所/博士(2018年)

摘要

此論文中我們提出低功耗、低面積之二維對稱型IIR濾波器。此論文包含Type-1、Type-2與Type-3 對角線對稱(diagonal symmetry)、四次旋轉對稱(fourfold rotational symmetry)、象限對稱(quadrantal symmetry)、八角形對稱(octagonal symmetry)之二維對稱型濾波器，Type-1、Type-3低功耗低成本之多組態二維對稱型濾波器，此兩種多組態二維對稱型濾波器可實現上述四種對稱型模式。此外我們還提出了應用德耳塔運算子在各種對稱式濾波器之架構，可更進一步在窄頻段濾波器得到更好的數值精密度並降低係數靈敏度。多組態二維對稱型濾波器，則可同時支援四種對稱型，達到面積最佳化的效果。其中Type-1四種對稱型與多組態濾波器皆經由Design Compiler與SOC Encounter完成TSMC180nm之晶片設計，並利用Prime Time完成功耗模擬。模擬結果顯示Type-1 對角線對稱、四次旋轉對稱、象限對稱、八角形對稱之二維對稱型濾波器與傳統無對稱型之濾波器相較下各節省16.77%、 36.30%、 22.90%與37.73% 的功耗；另一方面， Type-1多組態二維對稱型濾波器在各個對稱組態則各自節省11.01%、31.42%、17.53%與35.26%的功耗。Type-1多組態二維對稱型濾波器與Type-1獨立四種對稱型濾波器的面積總和比較起來減少了63.25%的面積，相較於傳統無對稱型之濾波器面積也減少了16.02%。

關鍵字

對稱式濾波器

並列摘要

In this dissertation, two-dimensional (2-D) VLSI digital filter architectures possessing various symmetries in the filter magnitude response are studied for the first time. For this purpose, Type-1, Type-2, and Type-3 power-efficient and cost-effective 2-D magnitude symmetry filter architectures possessing diagonal, four-fold rotational, quadrantal, and octagonal symmetries with reduced number of multipliers are given. For each Type (1-3), four structures incorporating each of the above symmetries are presented. In all 12 single symmetry structures are studied. Further, two power-efficient and cost-effective multimode 2-D symmetry filters are given. By combining the identities of four each of the Type-1 and Type-3 symmetry filter structures, the proposed Type-1 and Type-3 multimode 2-D symmetry filters can provide four different operation modes: diagonal symmetry mode (DSM), four-fold rotational symmetry mode (FRSM), quadrantal symmetry mode (QSM), and octagonal symmetry mode (OSM). Besides, the symmetry filter architectures using delta operator are also proposed for better numerical accuracy and lower coefficient sensitivity in narrow-band filter designs. According to ASIC implementation flow, Synopsys Design Compiler is employed to synthesize the Type-1 2-D filter designs in RTL level and Cadence SOC Encounter is adopted for placement and routing (P&R) in TSMC 0.18um. The power dissipation implementation result is measured via Synopsys PrimePower.
The Type-1 diagonal, four-fold rotational, quadrantal, and octagonal symmetry filter structures can attain power savings of 16.77%, 36.30%, 22.90%, and 37.73% with respect to that of the conventional 2-D filter design without symmetry. On the other hand, the Type-1 DSM, FRSM, QSM, and OSM modes can reduce power consumption by 11.01%, 31.42%, 17.53%, and 35.26% compared with that of the conventional 2-D filter design. The Type-1 multimode filter can result in 63.25% area reduction compared with the sum of the areas of the four individual Type-1 symmetry filter structures. Besides, we also provide Type-2 and Type-3 symmetry filter architectures with different structures and shorter critical paths.

並列關鍵字

symmetry filter

參考文獻

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