使用32位元低功率嵌入式處理器之高效能MP3解碼系統

Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core

辛威虢(Wei-Kuo Hsin)

指導教授 ： 黃俊達

國立交通大學/電機學院/電子工程系所/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00030

摘要

本論文提出一個高效能的MP3音訊解碼系統使用低功率之32位元嵌入式處理器ACARM9(Academic ARM9)。其一：此處理器有較佳的性能。此處理器以ARM V5E指令集實作，並且在乘法部份有更好的效能，此指令集能使用ADS(ARM Developer Suite) 的編譯器將高階程式語言(C,C++)編譯成組合語言，再將其組譯為可供 ACARM9 使用的機器語言，以顯示出此處理器的高使用性。其二：本論文提出一個完整的系統發展平台，此處理器之設計被燒錄在 FPGA之上，再使用 ARM926EJ-S Versatile發展板系統，以本處理器解碼MP3音訊資料，達到高效能的解碼速率及音訊同步化播放，完成MP3播放系統。

關鍵字

嵌入式處理器

並列摘要

This thesis presents the research result of an efficient MP3 decoder system using a 32-bit low-power embedded processor core, named ACARM9 (ACademic ARM9). The ISA (Instruction Set Architecture) of ACARM9 adopts the ARM V5E architecture but owns more efficient multiplication instructions. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the code of high level programming language (C, C++) written by users to the assembly code, and then can assemble the assembly code to the low level machine code for ACARM9 use. It indicates the high usability of ACARM9. Moreover, this thesis presents a methodology for platform-based design. The proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board. Then an MP3 decoder system, which is capable of providing high decoding rate and playing audio synchronously, is successfully implemented using the proposed platform.

並列關鍵字

mp3

參考文獻

[5] ARM, ARM926EJ-S Development Chip Reference Manual.

[6] ARM, ARM Architecture Reference Manual.

[18] ARM, ARM9E-S Core Revision: r2p1 Technical Reference Manual.

[23] ARM, PrimeCell Vectored Interrupt Controller (PL190)Revision: r1p2 Technical Reference Manual.

[27] Vijaykuinar Gurkhe, "OPTIMIZATION OF AN MP3 DECODER ON THE ARM PROCESSOR," TENCON 2003.