新穎長晶控制技術於積層型三維後段鰭式場效電晶之製程開發與其電性研究

Process Development and Device Electrical Investigation of Novel Location-Controlled Grain Technique for Monolithic 3D IC

張益睿(Yi-Jui Chang)

指導教授 ： 陳冠能

國立交通大學/電機學院/電子工程系所/碩士(2019年)

摘要

積層型三維積體電路(Monolithic 3D IC)是近年來半導體領域技術發展的重點研究對象之一，藉由IC的堆疊來縮短訊號傳遞的距離，並整合與增強整體晶片系統效能以及微縮晶片尺寸，以實現更快速、更便宜且低功耗的晶片。積層型三維積體關鍵技術中，低溫多晶矽薄膜電晶體（LTPS-TFT）技術扮演垂直堆疊的重要角色，傳統長晶製程中，高品質多晶矽薄膜之製作，其製程溫度需十分高溫，大幅高於後段製程所能容許溫度，導致底層元件損壞，因此近年來隨著多晶矽結晶製程的進步，以雷射結晶製程最被廣泛來製作低熱預算的多晶矽薄膜，雷射結晶製程可在不損壞底層元件條件下，於上層製作高品質之多晶矽薄膜以達成高效能的元件製作。然而，以雷射長晶製程所製作低熱預算的多晶矽薄膜雖可避免底層元件之損傷，但多晶矽之晶粒邊界在長晶過程中是隨機分佈於多晶矽薄膜中，因此對於電路佈局設計以及元件製作上有極大的困難，易導致在單一晶圓上其元件特性不均勻且良率下降，進而限制了其技術上的發展。
本篇論文成功研發出一種新穎長晶控制技術用於三維積層型後段鰭式場效電晶體(Monolithic 3D BEOL FinFET)，其透過陣列式奈米級孔洞(Cooling holes)之設計，可預先定義多晶矽長晶位置與大小，並於SiO2介電層上方沉積一層Si3N4介電層，透過Si3N4之材料特性，降低晶粒內晶粒邊界的產生，最後經由綠光奈秒雷射長晶技術(GNS-LC)進行熔融長晶，可以得到規則排列且無晶粒邊界之多晶矽長晶，其晶粒大小可以達到700nm。此項研究之優勢在於可預期性地避開晶粒邊界，將電晶體與電路製作於無晶粒邊界之矽薄膜中，藉此達到最佳的元件特性，提升電路品質與降低功耗。此外，本研究透過ANSYS熱傳模擬分析模擬綠光奈秒雷射長晶製程下之整體溫度分布，進行各項結晶現象分析，並從模擬結果證明底層元件的確在多晶矽結晶製程中並不會因為雷射結晶而超出其後段製程容許溫度400℃。

相較於傳統積層型三維積體電路，透過此長晶控制技術所製作之無晶粒邊界之後段鰭式場效電晶體，在元件電性表現上有相當優異的成果，其可以擁有良好的臨界擺幅（<80mV/decade）、低漏電電流以及高電流開關比(Ion/Ioff>107），在本論文中，新穎長晶控制技術於三維積層型後段鰭式場效電晶體被成功開發，其對於積層型三維異質整合具有卓越的潛力。

關鍵字

積層型三維積體電路 ； 鰭式場效電晶體 ； 陣列式奈米級孔洞 ； 綠光奈秒雷射 ； 長晶控制技術

並列摘要

Nowadays, the monolithic three-dimensional integrated circuit (Monolithic 3D-IC) is one of the key research in the development of the semiconductor industry. The distance of signal transmission can be decreased by stacking ICs. Besides, it integrates and enhances overall wafer system performance and minimizes the chip size to achieve faster, cheaper, and lower power chips. In the key technology of monolithic 3DICs, low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) technology plays a very important role in 3D stacking technology. In traditional crystallization process, so as to obtain a high-quality polycrystalline s film, the process temperature needs to be significantly higher than the BEOL allowable temperature, resulting in damage to the underlying components.
Therefore, in recent years, with the advancement of poly-silicon crystallization technology, green nanosecond pulse-laser crystallization technology is widely used for fabricating low temperature poly-silicon thin film transistors (LTPS-TFTs). This technology would be used for fabricating better polycrystalline silicon films on the top layer without damaging the bottom devices. However, the grain boundaries of the Poly-Si are randomly distributed during the laser crystallization. The low temperature poly-silicon thin film transistors (LTPS-TFTs) conversion characteristics would be affected by these grain defects, which cause uniformity issue of upper polysilicon devices. It is quite difficult for the layout designer to design the position of devices. Therefore, it limits the development of this technology.
In this thesis, a novel location-controlled-grain technique for monolithic 3D BEOL FinFETs was successfully fabricated. First of all, through the array design of the cooling holes, the position and size of the Poly-Si can be pre-defined. In addition, the HK dielectric layer would be deposited on the SiO2 dielectric layer to reduce internal grain boundary. Finally, the green nanosecond pulse-laser would be used to crystallize Poly-Si. It is possible to obtain the epi-like silicon film without any grain boundaries which are regularly arranged. The advantage of this method is that the layout can avoid grain boundaries expectedly. The transistors and circuits can be fabricated in a high-quality and grain boundary-free epi-like film to achieve optimized device electrical performance, thereby improving circuit quality and reducing power consumption. In addition, ANSYS heat transfer simulation was used to simulate the overall temperature distribution under the green nanosecond laser growth process and analyze the various crystallization phenomena. According to the simulation results, after laser crystallization, the temperature of underlying components is still below the allowable temperature 400 °C.
Compared with the conventional monolithic 3DICs, the grain-boundary free BEOL FinFETs were produced by this location controlled grain technology with excellent electrical performance. The electrical characteristics include better sub-threshold swing (<80mV/decade), Lower off current, and high Ion/Ioff ratio (>107). In this thesis, a novel location-controlled grain technique for BEOL FinFETs was fabricated successfully, which has great potential for monolithic three-dimensional heterogeneous integration.

並列關鍵字

Monolithic 3D-IC ； BEOL FinFETs ； Cooling holes ； Green nanosecond pulse-laser ； Location-Controlled Grain

參考文獻

Reference

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