應用於60GHz頻帶10Gbps單一載波基頻之脈波成形和同相與正交分量不平衡及直流偏壓準位偏移聯合補償設計

Design of Pulse Shaping Filter and Compensation Design of Transmitter IQ Mismatch and DC Voltage Offset for 10Gbps Single Carrier Baseband at 60GHz Band

團玉江(Doan Ngoc Giang)

指導教授 ： 周世傑

國立交通大學/電機學院/電機資訊國際學位學程/碩士(2019年)

摘要

在數位無線通訊中，系統的性能由兩個重要的測量值來測量，這兩個測量值是發射機的誤差向量幅度（EVM）和接收機的位元錯誤率（BER）。
脈衝整形濾波器（PSF）是數位通訊系統中必不可或少的原件之一，因為它有利於降低發送信號的帶寬頻率並消除符號間干擾（ISI）。然而，由於可以在實際電路中實現的係數有限，PSF通常會引入非理想效應，這會降低系統的EVM和BER。影響系統性能的另外兩個非理想效應是IQ失調和DC電壓偏移。這兩種效應通常由通訊系統中的低成本RF模擬電路引入，並且對系統性能具有很大影響。因此，IQ失調和DC電壓偏移的估計和補償對於任何通訊系統的設計來說都是極其重要的任務。
本文提出了一種PSF和IQ失調以及DC電壓偏移校準模組的設計，該模組能夠滿足IEEE 802.11ad標準規定的發送器EVM要求，並且在每千個發送位的條件下，接收器BER要求小於3個錯誤位。採用16 QAM調製方案，訊雜比（SNR）為17dB。
PSF和IQ失調以及DC電壓偏移校準模組的硬體設計用於4倍平行數據處理，能夠在625MHz工作時脈下工作。這兩個模組的設計允許整個系統在使用16 QAM調製時可以存檔2.5GHz的符號率和10Gbps的物理數據速率。我們嘗試通過根據模擬結果選擇優化的字長來減小設計的面積和功耗。該設計採用台積電提供28nm HPC＋的技術合成，生成閘級網表。通過運行閘級模擬驗證了設計的功能。
對於複雜的無線通訊晶片，由於晶片製造工藝的高成本，功能測試在下線階段之前是非常重要的。設計的功能測試將有助於減少晶片製造後失效功能的可能性。在本論文中，我們想要使用NI的設備為我們的基頻處理器的發送器端引入測試程序。通過這樣做，我們不僅能夠再次驗證基頻設計的功能，還能夠證明我們的設計能夠成功的與通訊系統的其他原件一起運作，例如DAC / ADC和RF電路。

關鍵字

脈衝整形濾波器 ； 誤差向量幅度 ； 位元錯誤率 ； IQ失調 ； DC電壓偏移 ； 單一載波基頻之 ； 60GHz頻帶

並列摘要

In digital wireless communication, the performance of the system is measured by two important measurement values which are Error Vector Magnitude (EVM) for the transmitter and Bit Error Rate (BER) for the receiver.
Pulse Shaping Filter (PSF) is one of the essential components in the digital communication system due to its benefit of reducing bandwidth frequency of the transmitted signal and eliminating Inter-Symbol Interference (ISI). However, because of the limited number of coefficients that can be implemented in the real circuit, PSF usually introduces non-ideal effects that degrade both EVM and BER of the system. The two other non-ideal effects which affect the performance of the system is IQ mismatch and DC voltage offset. These two effects are usually introduced by low-cost RF analog circuit in the communication system and have a large influence to the system performance. Therefore, estimation and compensation of IQ mismatch and DC voltage offset are an extremely important task for the design of any communication system.
This thesis proposes a designed of PSF and IQ mismatch and DC voltage offset calibration module which is able to meet transmitter EVM requirement stated by IEEE 802.11ad standard and receiver BER requirement of less than 3 error bits per every one thousands of sent bits under condition of using 16 QAM modulation scheme and Signal to Noise ratio (SNR) of 17dB.
The hardware of PSF and IQ mismatch and DC voltage offset calibration module are designed for 4X parallelism data processing and are able to work at the 625MHz operating clock. The design of these two modules allows the overall system can archive the symbol rate of the 2.5GHz and a physical data rate of 10Gbps when 16 QAM modulation is used. We try to reduce the area and power of design by choosing the optimized word-length based on the simulation result. The design is synthesized using 28nm HPC+ technology provided by TSMC to generate gate-level netlist. The function of design is verified by running gate-level simulation.
For a complicate wireless communication chip, function testing is extremely important before the tape-out stage due to the high cost of the chip manufacturing process. Function testing of design would help reduce the possibilities of failed function after the chip is made. In this thesis, we would like to introduce a testing procedure for the transmitter side of our baseband processor using equipment from National Instrument (NI). By doing this, we are able not only to verify again the function of baseband design but also to prove that our design can successfully work with other components of the communication system, for example, DAC/ADC and RF circuit.

並列關鍵字

Pulse Shaping Filter ； Error Vector Magnitude ； Bit Error Rate ； IQ Mismatch ； DC Voltage Offset ； Single Carrier Baseband ； 60GHz Band

參考文獻

[1] W.-C. Lee, "Phase Noise-Robust Synchronization and Phase Noise Compensation Design for 10Gbps Single Carrier Baseband Receiver at 60 GHz Band," NCTU, 2018.

[2] U. F. C. Commission, "Millimeter Wave Propagation: Spectrum Management Implications," Bulletin Number 70, p. 6, July 2017.

[3] W.-H. S. Chen-Jui Hsu, "Joint Calibration of Transmitter and Receiver Impairments in Direct-Conversion Radio Architecture," IEEE Transactions on Wireless Communication, 2011.

[4] IEEE, "Amendment 3: Enhancements for Very High Throughput in the 60 GHz Band," in Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std 802.11ad, 2012.

[5] J. B.Anderson, Digital Transmission Engineering, 2 ed., IEEE, 2005.