應用於生醫系統之高效能學習計算架構及其實現

An Efficient Learning Computation Architecture and Implementation for Biomedical System Application

呂宗哲(Tsung-Che Lu)

指導教授 ： 范倫達

國立交通大學/資訊學院/資訊科學與工程研究所/博士(2019年)

摘要

本篇論文旨在探討高效能生醫學習計算架構的關鍵子系統。一般來說，學習計算系統的挑戰主要包含：1)訊號品質、2)高效能、以及3)在線處理能力。因此，本論文在高效能生醫學習計算架構的兩個關鍵子系統上，提出對應的架構與實現以克服前述之限制。
在生醫訊號數位化子系統上，我們專注於逐漸趨近式(SAR)類比數位轉換器(ADC)之架構與實現，其中共包含兩個研究。在第一個研究中，我們提出一個綜合低電壓、低取樣頻率與低數位-類比轉換器(DAC)電容之方法以達成低功耗之性能。同時，我們也提出低漏電之增強式開關(Leakage Reduction Boosted Switch, LRBS)，以克服前述方法造成之漏電，並進而提升以失真比(SNDR)與有效位元(ENOB)衡量之訊號品質。該研究以台積電(TSMC)之0.18微米製程製造之雛型晶片，其在0.5 V的供應電壓與1 KS/s的取樣率下，量測結果之功耗為2.5nW，而訊號失真比(SNDR)與品質因數(FOM)分別為56.05 dB與6.8 fJ/conversion-step。在第二個研究中，我們基於第一個研究的成果，提出提高取樣率之低漏電增強式開關(Sample-Rate-Enhanced Leakage Reduction Boosted Switch, SRE-LRBS)，以更進一步將取樣率由1 KS/s提高至100 KS/s，並同時保有低漏電之性能。另外，我們在關鍵的比較器上採用交叉耦合的自我基極偏壓(Cross-Coupled Self-Body-Bias, CCSBB)，以提升在噪聲限制下之比較器操作頻率。該研究以台積電(TSMC)之0.18微米製程實現下，量測9顆晶片的平均結果顯示，在0.6 V的供應電壓與100 KS/s的取樣率下，功耗為490 nW，有效位元(ENOB)為9.00 bit，無雜散動態範圍(SFDR)為71.70 dB，其品質因數(FOM)為9.56 fJ/conversion-step。
在生醫訊號計算子系統上，我們主要專注於高效能快速獨立成分分析(FastICA)演算法之架構與實現，其中包含了兩個研究。第一個研究提出一基於浮點(Floating Point)運算之低成本快速獨立成分分析(FastICA)架構。透過兩個被重複使用的計算單元(PU)與基於格蘭史密特(Gram-Schmidt)的白化(Whitening)運算，我們可以有效降低硬體複雜度以達成低成本的目標。其中，包含可變頻道數(Variable Channel)、重新參照(Re-reference)、同步平均(Synchronized Average)與移動平均(Moving Average)的多功能(Multi-Function)特性更是提升了使用的彈性。此研究我們使用台積電(TSMC)之90奈米製程，以特殊積體電路(ASIC)實現，晶片尺寸為1.43 mm^2。其在供應電壓為1V時，操作在100MHz下之功耗為19.4 mW。第二個研究展示了一個硬體相容的在線快速獨立成分分析 (FastICA)架構與實現。其中之在線在線快速獨立成分分析 (FastICA)演算法採用了資料重疊(Data Overlapping)、垃圾偵測(Garbage Detection)、頻道重排(Channel Permutation)、以及基於慣量控制的權重更新(Momentum-Controlled Weight Update)，以避免分離訊號在不同時間區塊下的通道次序(Channel Order)改變。該研究使用台積電(TSMC)之 90奈米製程實現的結果，其晶片面積為1.469x1.469 mm^2，在供應電壓1V與時脈100 MHz下之功耗為65mW.

關鍵字

生醫系統 ； 學習計算架構 ； 逐漸趨近式類比數位轉換器 ； 快速獨立成分分析 ； 高效能 ； 在線處理能力

並列摘要

In this dissertation, the key sub-systems for the efficient biomedical learning computation system are explored. Generally, the main challenges of the learning computation system include: 1) high signal quality, 2) high efficiency and 3) on-line processing capability. Therefore, we propose the corresponding architectures and implementations in order to tackle these limitations for two key sub-systems of the biomedical learning computation system.
For the biomedical signal digitizing sub-system, we focus on successive-approximation (SAR) analog-to-digital converter (ADC) architecture and implementation. Two studies are proposed. In the first study, we proposed an approach that combines low voltage, low sampling rate, and low digital-to-analog converter (DAC) capacitance to attain very low power performance. Meanwhile, the Leakage Reduction Boosted Switch (LRBS) is proposed to alleviate the leakage caused by the aforementioned low-power approach to improve the signal quality regarding signal-to-noise-and-distortion ratio (SNDR) and effective number of bits (ENOB). The measurement results of the prototype chip fabricated with TSMC 0.18μm process show a power consumption of 2.5 nW with 0.5 V supply at 1 KS/s. The measured SNDR and resultant figure of merit (FOM) are 56.05 dB and 6.8fJ/conversion-step, respectively. The second study based on the first study proposes Sample-Rate-Enhanced Leakage Reduction Boosted Switch (SRE-LRBS) to further improve the sampling rate from 1 KS/s to 100 KS/s while maintaining the low-leakage performance. Meanwhile, we adopt Cross-Coupled Self-Body-Bias (CCSBB) in the comparator to overcome the speed limitation for the noise requirement. The prototype ADC is fabricated with TSMC 0.18μm process. The average measurement results on nine chips show power consumption, ENOB, SFDR, FOM are 490 nW, 9.00 bit, 71.70 dB, 9.56 fJ/conversion-step, respectively, with 0.6 V supply voltage at 100 KS/s.
For the biomedical signal computation sub-system, we focus on efficient fast independent component analysis (FastICA) architecture and implementation, where two studies are involved. The first study proposes a cost-effective floating-point FastICA architecture. Through two new reused PUs with Gram-Schmidt based whitening, the hardware complexity can be reduced to attain the cost-effective target. Multi-function including variable-channel FastICA, re-reference, synchronized average, and moving average processing are supported in this study to improve the flexibility. The application-specific integrated circuit (ASIC) implementation results in TSMC 90nm process show that the die area is 1.43 mm^2 and power consumption is 19.4 mV at 100 MHz with 1.0 V supply voltage. The second study shows a hardware-compatible on-line FastICA architecture and implementation. In the on-line FastICA algorithm, data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes are adopted to avoid channel order change of the decomposed source signals over different time slots. The hardware implementation in TSMC 90nm process results show that a core area of 1.469x1.469 mm^2 and the power consumption is 65 mW at 100 MHz with 1.0V supply voltage.

並列關鍵字

biomedical system ； learning computation architecture ； SAR ADC ； FastICA ； high efficiency ； on-line capability

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