隨著無線通訊朝向毫米波頻帶發展,類比及射頻元件的設計變得更為艱困,因而對收發機造成嚴重的性能衰退。儘管已有研究提出一些數位基頻估測與補償技術,但仍會有些許的殘餘量,使得星座圖扭曲且效能不如預期。傳統通訊補償的方法大致藉由數學推導及分析來進行估測及補償。而有別於以往之研究方法,在此論文中基於機器學習的方法,使用可行的向量支援機器以緩解剩餘的不理想效應所造成的性能損失。基於IEEE 802.11ad及10 Gbps傳輸速率的標準下,從系統層面,並且考慮類比前端元件及射頻模組的效應,進行整體效能分析以及架構設計。 除此之外,資料傳輸率的需求也隨著5G世代而大幅增加,因此,此論文也提出非正方形的調變方法及設計,並且能使得調變階數在毫米波嚴峻的非理想類比及射頻模組之下,提高至64QAM以增加資料吞吐率。此調變方式主要是針對相位雜訊在高調變階數時所造成的衰退來進行設計,同時利用支援向量機取得非線性的決策邊界。 在硬體架構設計上,使用了bit-based的組成以降低訓練的時間以及複雜度。此外,儲存訓練資料庫的記憶體也考慮了硬體共用,以降低硬體負擔。此論文使用TSMC 28nm HPC Plus製程並採用四倍平行架構達到2.5GHz的碼片率,在16QAM調變下能使實體層資料傳輸率達到10Gbps。
As wireless communication is explored toward mm-wave frequency band, it is more difficult to design analog front-end components and radio frequency modules, which consequently severely degrades the performance of transceiver baseband system. In spite of existing estimation and compensation technique on digital baseband that has been proposed, some residual amounts of non-ideal effects are still remained and hence makes constellation distorted and even cannot meet the expectation. Different from traditional compensation methods and research, via mathematical derivation and analysis, the applicable machine learning method, support vector machine is adopted in this thesis to mitigate the performance loss resulted from the residual non-ideal effects. The whole architecture is analyzed and designed thoroughly based on IEEE 802.11ad and 10 Gbps from system point of view, considering effects from analog front-end and radio-frequency modules. In addition, as the demand of data transmission rate is significantly getting higher for 5G generation, a nonuniform modulation scheme is also proposed in this thesis. Under the rigid conditions of non-ideal analog and radio frequency components in millimeter wave band, the modulation order is increased to 64QAM for higher data throughput data. It is aimed at the mitigation to the severe degradation caused by phase noise in high order modulation. Meanwhile, support vector machine is adopted to derive nonlinear decision boundaries. The bit-based composition is adopted in hardware architecture implementation to reduce the training latency and complexity. Besides, memories for saving training data set are shared between each sub-model to ease the cost on hardware. The architecture is based on TSMC 28nm HPC Plus technology and takes 4-times parallelism to achieve 2.5 GHz chip rate. The target physical data transmission rate, 10 Gbps, is accomplished under 16 QAM modulation scheme.