複晶矽奈米線通道在雙閘極倒T型結構上之製作與特性分析

Fabrication and Characterizations of Inverse-T Double-Gated Devices with Poly-Si Nanowire Structure

戴君帆

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00703

摘要

在本篇論文中，利用邊襯蝕刻技術製作具有雙閘極結構的複晶矽奈米線通道。閘極耦合效用能有效改善基本電性與寫入/抹除特性。在奈米線通道和雙閘極結構下，藉由增強閘極的控制能力，能有效抑制短通到效應。此外，較好的次臨界擺幅與較大的打開電流也能因此獲得。小體積奈米線通道和雙閘極結構，在不同操作條件下，可輕易地調控臨界電壓。以氮化矽為堆積介電層結構下，能有效降低漏電流。
利用雙閘極結構，研究在不同操作條件下的寫入，抹除和讀取特性。除此之外，本論文亦展示在此雙閘極結構中，1、0狀態下的電壓差異與寫入/抹除效率的調控。即便如此，可靠度特性(例如：資料保存、元件耐久性)並不如預期。穿隧氧化層與奈米線通道結構的替代選擇，將可使可靠度獲得顯著的改善。

關鍵字

雙閘極 ； 奈米線

並列摘要

In this thesis, poly-Si nanowires(NWs) with independent double-gated(DG) configuration are fabricated by a simple sidewall spacer techniques. Gate-to-gate coupling effect facilitates the basic electrical characteristics and programming/erasing (P/E) characteristics. NWs and DG structure effectively mitigate short-channel effect by enhancing the gate controllability. Besides, better subthreshold swing and higher on-current can be achieved as well. Threshold voltage (VTH) is easily modulated in different operating modes due to the small volume of NWs, together with the DG structure. In addition, off-state current is suppressed in the fabricated devices with O/N/O stack dielectrics.
Programming, erasing and reading under different manipulation of the DG structures are studied. In addition, VTH windows and modulation of the P/E efficiencies with DG structure are demonstrated in this study as well. However, the reliability characteristics (i.e., retention, endurance) are poorer than expected. Substitutes for tunneling oxide dielectrics and alternatives to the NW structures are needed in order to achieve better the reliability characteristics.

並列關鍵字

double-gated ； nanowire

參考文獻

[1-1] G. Moore,” Progress in digital integrated electronics,” IEDM Tech. Digest., pp. 11-13, 1975.

[1-2] Paul S. Peercy,“ The drive to miniaturization,” Nature, vol. 406, p.1023-1026, 2000.

[1-3] Y. Cui, Z. Zhong, D. Wang, W. Wang, C. M. Lieber,” High performance silicon nanowire field effect transistors, ” Nano Lett., vol. 3, no. 2, pp. 149-152, 2003.

[1-4] Sang-Mo Koo, Q. Li, M. D. Edelstein, C. A. Richter, and E. M. Vogel, ” Enhanced channel modulation in dual-gated silicon nanowire transistors,” Nano Lett., vlo.5, pp.2519-2523, 2005.

[1-5] Jean-Pierre Colinge,“ Multiple-gate SOI MOSFET,” Solis-State Electronics, vol.48, pp.897-905, 2004.