氧化鋁/二氧化鉿交錯層應用於非揮發性記憶體特性研究

本論文提出以原子層沉積法沉積氧化鋁/二氧化鉿交錯層作為快閃式非揮發性記憶體的電荷儲存層。製作的電容結構以及薄膜電晶體結構，採用高介電常數材料氧化鋁作為電荷阻擋層，並分別使用高功含數材料白金與p+多晶矽作為電容結構元件與多晶矽薄膜記憶體結構元件之閘極，以降低元件抹除時背部電子注入與等效厚度。論文討論記憶體的基本電性，包括記憶窗口、寫入/抹除速度、電荷保持力、耐久性與抗擾性，並且進一步討論製程差異所造成的電性影響與原因，包括氧化鋁/二氧化鉿交錯層重複次數、形成奈米顆粒退火時間與電荷阻擋層厚度的改變。在電容部份，發現經過攝氏900度/60秒退火後的元件記憶窗口較經過攝氏900度/30秒退火後的元件大，而此攝氏900度/60秒退火會使氧化鋁些微結晶，造成元件抹除速度下降，而將氧化鋁加厚為20奈米，則可大幅降低漏電。此記憶體元件在寫入/抹除條件為15V/1秒時有6V的記憶窗口，且經過105秒後仍有百分之83，並在耐久性與抗擾性上有不錯的特性。在多晶矽薄膜記憶體部份，閘極介電質與電容元件相似，但因改將氧化鋁作為穿隧氧化層，經過高溫退火後有結晶狀況，因而導致許多負面效應。總結而言，使用氧化鋁/二氧化鉿交錯層，有不錯的電荷儲存力，但必需搭配可靠的穿隧氧化層與電荷阻擋層，使元件在高溫製程後有良好的可靠度，因此值得進一步研究。

關鍵字

記憶體

並列摘要

In this thesis, we proposed an Al2O3/HfO2 nano-laminate deposited by atomic layer deposition (ALD) method as the trapping layer of the flash type non-volatile memory. Both capacitor and thin-film transistor (TFT) structures were prepared. In order to suppress the back-side injection during erase period and to reduce the equivalent oxide thickness, high work-function gate (platinum for capacitor and P+ poly-Si for TFT) and Al2O3 blocking layer was utilized, respectively. The whole memory characteristics including memory window, program/erase speed, retention, endurance, and disturbance were evaluated and discussed in the thesis. Furthermore, the effects of process conditions, including the number of Al2O3/HfO2 nano-laminate periods, post-deposition annealing (PDA) condition, and blocking layer thickness were also studied. On the capacitor samples, a 900C/60sec PAD can result in a larger memory window than a 900C/30sec PAD. But the erase speed degrades due to crystallization of the Al2O3 blocking layer. Increasing Al2O3 blocking layer thickness from 10 nm to 20nm can strongly reduce the leakage current. Therefore, a 6V memory window after 15V program/erase (P/E) operation for 1 sec can be achieved. About 83% of the window still remains after 105 sec. Well endurance and disturbance properties are also observed. On the TFT-memory samples, the structure of the dielectric stack is similar to that on the capacitor samples, the main difference is the SiO2 tunneling layer was replaced by Al2O3. The TFT structure exhibits faster program speed. However, because of the crystallization of the Al2O3 tunneling layer, several drawbacks such as poor retention due to charge loss through the Al2O3 tunneling layer, poor endurance, and poor gate disturbance. In conclusion, the Al2O3/HfO2 charge trapping layer proposed in this thesis exhibits good electrical performance and storage capability. The main issue of this structure would be the quality of both the tunneling and blocking layers. These layers should behave excellent thermal stability during the proceeding fabrication process and is worth further researches.

並列關鍵字

memory

參考文獻

[1] D. Kahng and S. M Sze, “A floating gate and its application to memory devices”, IEEE Trans. Electron Devices, vol.14, pp.629-629, 1967

[2] J. D. Blauwe, “Nano-crystal Non-volatile Memory Devices,” IEEE Trans. Nanotechnology, vol.1, pp. 72-77, 2002

[4] J. D. Lee, S. H. Hur, and J. D. Choi, “Effects of floating gate interferences on NAND Flash memory cell operation”, IEEE Electron Device Letters, vol.23, pp. 264-266, 2002

[6] J. Bu, and M. H. White, “Effects of Two-Step High Temperature Deuterium Anneals on SONOS Non-volatile Memory Devices,” IEEE Electron Device Letters, vol.22, pp.17-19, 2001.

[8] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-k charge trapping layer,” in VLSI Symp. Tech. Dig., pp. 27-28, 2003

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氧化鋁/二氧化鉿交錯層應用於非揮發性記憶體特性研究

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