一種具懸浮奈米通道之元件製作與其分析模型

在本論文中，我們成功地製作了具懸浮式奈米通道之薄膜電晶體(suspended-NW-channel TFTs)。懸浮奈米線通道主要是利用邊襯(sidewall spacer)作為電晶體的通道，此一結構可由低成本的反應式離子蝕刻(RIE)技術製作完成。在實驗中，我們利用一組新光罩，變化元件結構的各項參數，最後再根據量測結果與我們所發展建立的一個理論模型結果做比較。如先前的研究[37, 40] 所指出，此一結構有著極低的次臨界擺幅(subthreshold slope)、以及一遲滯窗口(hysteresis window)。藉由我們自行發展推導的分析模型，可以有效計算出不同條件下所對應的擺入電壓(Vpi)與擺出電壓(Vpo)；此外，我們也可以藉由此模型，了解到擺入時次臨界擺幅極低的主因。因此，此一模型可以成功地解釋我們的基本電性。最後，我們也針對改變量測機台的參數，來觀察此一結構受到充電時間對於擺入電壓、擺出電壓的影響，並且觀察到當量測速度放慢時，會有複雜的振動現象(oscillation phenomenon)出現。另一方面，為了有效降低擺出時受到凡德瓦力(van der Waals force)的影響，我們設計了一種含有奈米點(Si nano dots) 嵌入之閘極介電層的新結構，利用此結構有效的使接觸面變得粗糙，藉以降低接觸面積，進而減少凡德瓦力的影響，可使擺入電壓與遲滯窗口有效地減少。

關鍵字

奈米線；薄膜電晶體；模型；多晶矽

並列摘要

In this thesis, we have fabricated and studied the suspended-nanowire (NW)-channel TFTs. The devices use the sidewall-spacer etching technique to form the poly-Si NW channel of transistors, and the whole device structures can be formed by a simple and low-cost fabrication flow. In the experimental work, we’ve designed a new mask set which contains a number of devices with varying structural parameters. Results of the fabricated devices generated from these designs could help verify the accuracy of a theoretical model developed in this thesis. From our previous work [37, 40], we have learned that such kind of devices would show ultra-low subthreshold swing (S.S.) and hysteresis characteristics. Based on our analytical model, we can calculate the Vpi and Vpo and predict most of the effects of structural parameters and operation conditions. It is also helpful for us to understand the origin of the ultra-low S.S. when pull-in phenomenon occurs. Moreover, basic electrical characteristics of the device can be well described. Lastly, by changing some parameters of the measurements to vary the gate sweeping rate, we have explored the effects of the charge time on Vpi and Vpo. It is also interesting to observe complex oscillation phenomena when the sweeping rate is slow. Finally, we’ve proposed a new structure which has Si nano dots embedded in the gate nitride in an effort to lower the van der Waals force as the channel is in contact with the gate nitride. Using this structure we can effectively roughen the surface of the gate nitride which in turn would lower the effective contact area and thus reduce the van der Waals force.

並列關鍵字

nanowire ； thin film transistor ； modeling ； poly silicon

參考文獻

[1] G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114-117, 1965.

[2] J. S. Kilby, "Invention of the integrated circuit," IEEE Trans. on Electron Devices, vol. 23, no. 7, pp. 648-653, 1976.

[3] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-281, 2001.

[4] R. H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: from bulk to SOI to bulk," IEEE Trans. on Electron Devices, vol. 39, no. 7, pp. 1704-1710, 1992.

[6] X. Duan, Y. Huang, and C. M. Lieber, "Nonvolatile memory and programmable logic from molecule-gated nanowires," Nano Lett., vol. 2, pp. 487-490, 2002.

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一種具懸浮奈米通道之元件製作與其分析模型

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