動態臨界電晶體之精簡物理模型與應用

Compact Physical-Based Model and Applications of Dynamic-Threshold-Metal-Oxide-Semiconductor

王冠迪(Kuan-Ti Wang)

指導教授 ： 趙天生

國立交通大學/理學院/電子物理系所/博士(2011年)

https://doi.org/10.6842/NCTU.2011.00319

摘要

首先，我們將傳統的最大電導外插法萃取臨界電壓值的方法應用在動態臨界電晶體上，成功的利用實驗結果證明此方法亦可應用在動態臨界電晶體上；接著利用等效電位的概念，我們用能帶模型來表示動態臨界電晶體藉由控制閘極與源極的電位而順利達到接近完美的通道電位控制；更進一步地，我們提出一種新穎的基板效應常數萃取方式—m模型，相較於傳統必須量測不同基板電壓所呈現的臨界電壓變化來繪圖萃取曲線斜率的複雜方式，此新穎的方法可以快速的在單一元件上萃取出基板效應常數，並用來設計動態臨界電晶體臨界電壓。此外，動態臨界電晶體相對於傳統電晶體可以有更好的抵抗短通道效應的能力(~9%改進)，這是由於從源極與汲極端所產生的關鍵穿遂電場可以透過順向基板電壓的控制而降低；分離式電容電壓的量測方式則證明動態臨界電晶體在相同的反轉層電荷密度下，能夠使載子遷移率有32%增進，主要原因是順向基板效應有效降低空乏區電荷；利用金屬閘極(TaC、TiN)取代傳統多晶矽閘極(Poly)來抑制閘極空乏區的效果可以有效降低等效氧化層厚度約4埃；彈道傳輸係數對順向基板電壓的特性結果則顯示動態臨界電晶體在抑制汲極端引起能障降低的效應過程中，亦將同時降低彈道傳輸係數；而射入速度則可以隨著載子遷移率的增加而上升。
此外，我們提出一種新穎的動態臨界源極射入法在具有隱藏式選擇性閘極之快閃記憶體元件於NOR電路陣列上，此元件不僅製程簡單也符合一般數位邏輯CMOS產品中的嵌入式非揮發性記憶體應用。在論文中，我們利用ISE電腦輔助設計模擬軟體結合記憶體製程與熱電子注入模型的研究成果來詳細的說明此動態臨界源極射入法的寫入機制。模擬的結果顯示當隱藏式選擇性閘極記憶體操作在動態臨界源極射入法下將受幾個重要的因素所影響，其中包含了寫入電流量的大小與在隱藏式選擇性閘極記憶體中性區間的橫向電場與垂直電場。因此，我們比較在此記憶體結構中三種不同操作模式下的寫入效率，分別為：傳統源極射入法、基板偏壓增進源極射入法與動態臨界射入法。從量測實驗資料與電腦輔助模擬結果中可以發現，相較於傳統源極射入法，動態臨界射入法能同時大幅度的增加寫入電流量(~450%)與中性區間的最大橫向電場量值(~6%)，進而擁有較高的寫入效率。最後，我們利用動態臨界模式來完成具高效能(PGM=200ns/ERS=5ms)而低功率消耗(~25%降低)的單細胞二位元多層級操作，藉著利用動態臨界源極射入法的操作，多層級操作可以有更好的臨界電壓感測分佈區間、較低的單細胞二位元效應、優異的耐久力特性與良好的資料保存力。
最後，我們探討了操作溫度對動態臨界電晶體的影響，發現驅動電流對閘極偏壓變化中有一零溫度係數點(Zero-Temperature-Coefficient Point)，此零溫度係數點的發生，主要是因為臨界電壓與載子遷移率的互相補償結果；同時，當此動態臨界電晶體操作在低溫環境中，則可以降低關閉電流(off-current)，主要的原因是當元件隨著操作環境溫度降低時，本質載子密度會隨之下降(ni)，造成臨界電壓值上升；而低溫下(-50oC)的驅動電流則可以有1.4倍的提升。因此，正確的預測零溫度係數點將有助於操作動態臨界電晶體於不同環境溫度的應用，因此我們提出了一種新穎的動態臨界電晶體之零溫度係數模型來預測其操作點，可以非常準確的將誤差值降低在2%左右，其中短通道元件必須考慮汲極端偏壓降低能障效應對溫度與臨界電壓變化的影響。從實驗結果與理論模型上，亦可發現從固定基板偏壓的零溫度係數模型延伸至動態臨界電晶體上的零溫度係數模型是有一致性的結果，藉著將元件物理參數對操作環境溫度的影響詳加考慮，可以藉由適當的調整金屬功函數、基板效應常數與動態基板電壓對閘極偏壓的變化值來設計出動態臨界電晶體所需要的零溫度係數點。

關鍵字

動態臨界電晶體 ； 新穎萃取基版常數模型 ； 動態源極射入法 ； 零溫度係數模型

並列摘要

First, we use the maximum transconductance linear extrapolated method to extract VTH of DTMOS. It can largely reduce drafting time of extracting VTH of DTMOS by using this method. Furthermore, we lead the equivalent potential concept into DTMOS to indicate the channel potential control ability of both gate and source terminals with using band diagram, simultaneously. It deduces the m-model for extracting body effect coefficient without complicated variable substrate bias and fitting process. In addition, the penetration electric field from drain/source can be suppressed by the forward body bias of DTMOS, especially for short channel device. As a result, it improves the short channel effect (~9%) in DT technology due to decreasing of charge sharing effect. Then, we use split C-V to extract the effective mobility of DTMOS. Comparing to normal device, the higher mobility (~32%) of DTMOS can be attributed to the decreasing of normal electrical field for minor depletion region. The effect oxide thickness about 4 A of DTMOS can be reduced by using metal gate (TiN、TaC) to replace poly gate. It achieves by eliminating poly gate depletion. Besides, we prove that DTMOS owns the lower ballistic transport coefficient with higher injection velocity from source terminal due to its suppression of DIBL effect.
For the first time, high-performance with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory device, with multilevel and 2-bit/cell operation. The DTSSI programming mechanism was thoroughly investigated using the Integrated Systems Engineering (ISE) TCAD simulation tools combining the fabrication procedure and physical models. Results show the major factors affecting the DTSSI technique, including the supply current, and the lateral and vertical electric fields between the neutral-gap regions in the WSG-SONOS memory cell. Moreover, a programming mechanism for conventional source-side injection (Normal-mode), substrate-bias enhanced source-side injection (Body mode) and dynamic-threshold source-side injection (DT mode) of wrapped-select-gate SONOS (WSG-SONOS) memory is also developed with 2-D Possion equation and hot-electron simulation and programming characteristics measurement for NOR flash memory. Compared with traditional SSI, the DTSSI mechanisms are enhanced in terms of lateral acceleration electric field (~6%) and supply current (~450%) in the neutral gap region, resulting in high programming efficiency. It also provides lower power consumptions (~25% decrease). Finally, the high-performance (PGM=200ns/ERS=5ms) with low supply current in DT mode is used to achieve the multilevel and 2-bit/cell operation. Using the DTSSI enables easy extraction of the multilevel states with tight VTH distribution, nearly negligible second-bit effect, superior endurance characteristics, and good data retention.
Finally, we discuss DTMOS with regard to operation temperature effect. We find a zero-temperature-coefficient point with no current variation at elevated temperature in DT mode operation. The main reason is that compensation between threshold voltage and mobility at elevated temperature. Once operating the device with higher gate voltage than ZTC point, the phonon effect would degrade on current of device. On the contrary, the lower operation gate voltage than ZTC point would enhance the driving current due to its low threshold voltage at higher operation temperature. The decrease of threshold voltage is result from the increase of intrinsic density of material at elevated temperature. As a result, predicting the location of ZTC point precisely is very important to design device at different operation temperature. It can help to perform the circuit more stable and work well. Here, we propose a clear and simple ZTC point modeling of DTMOS with considering physical insights carefully. Using our DTMOS ZTC modeling, the mismatch value between our model and experimental data, no matter long channel or short channel device, can be reduced lower than 2%. Furthermore, the ZTC point of DTMOS can also be consistent by extracting from fixed body bias experimental data. It shows that optimum ZTC point of device can be adjusted by the body effect coefficient, work function and alpha ratio. Consequently, our model provides a design guideline for green DT technology.

並列關鍵字

DTMOS ； m-Model ； Dynamic-Threshold Source-Side-Injection ； Zero-Temperature-Coefficient Model

參考文獻

Chapter 1

[1.2] S. H. Lo, D. A. Buchanan, Y. Taur and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 209-211, 1997.

[1.3] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, “High-K/Meta-Gate Stack and Its MOSFET Characteristics,” IEEE Electron Device Lett., vol. 25, no. 6, pp. 408-410, 2004.

[1.5] M. Yamaguchi, T. Sakoda, H. Minakata, S. Xiao, Y. Morisaki, K. Ikeda and Y. Mishima. “Formation of HfSiON/SiO2/Si-Substrate Gate Stack With Low Leakage Current for High-Performance High-k MISFETs,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 923-925, 2006.

[1.6] S. Agrawal and J. G.. Fossum. “On the Suitability of a High-k Gate Dielectric in Nanoscale FinFET CMOS Technology”, IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1714-1719, 2008.