應用於生醫訊號紀錄之低耗能連續近似式類比數位轉換器設計

本論文提出一低功率消耗的連續近似式類比數位轉換器應用在生醫訊號測量。本論文中提出了一新的切換方式，能有效地降低續近似式類比數位轉換器所需的切換能量。設計規格為100KS/s、12位元及10KS/s、8位元的類比數位轉換器。採用UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process的製程來實現。類比數位轉換器的模擬結果在100KS/s、12位元模式下訊號對雜訊諧波比為69.7dB、有效位元為11.28位元，在10KS/s、8位元模式下訊號對雜訊諧波比為48.4dB、有效位元為7.75位元。所消耗的功率分別為5.42uW與3.12uW，晶片佈局面積為1145um*951um。

關鍵字

連續近似式類比數位轉換器；生醫訊號量測系統

並列摘要

A low power Successive Approximation Analog-to-Digital Converter (SAR ADC) is presented. This thesis presents a new switching procedure which with low switching energy. The design is a 100KS/s、12 bit resolution and 10KS/s、8bit resolution analog-to-digital converter, using UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process. The simulation results show that the ADC, under 100KS/s and 12-bit mode, achieves an SNDR of 69.7dB,and the resultant ENOB is 11.28bits. Under 10KS/s and 8-bit mode, it achieves an SNDR of 48.4dB, and the resultant ENOB is 7.75 bits. The power consumption of the ADC converter in 12-bit and 8-bit mode is 5.42uW and 3.12uW, respectively. Finally, the chip area is 1145um*951um.

並列關鍵字

Successive Approximation Analog-to-Digital Converter ； Biomedical Signal Recording System

參考文獻

[1] D. A. Johns and K. Martin , “Analog Integrated Circuit Design,” John Wiley and Sons Inc., 1997.

[2] F. Maloberti, “Data converters,” Springer Press, 2007.

[6] R. J. Baker, “CMOS Circuit Design Layout and Simulation, 2nd Edition,” IEEE Press, 2005

[7] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” IEEE Journal of Solid-State Circuits, vol. 1, pp. 184 - 187, 2005.

[8] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 731-740, 2010.

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應用於生醫訊號紀錄之低耗能連續近似式類比數位轉換器設計

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