奈米互補式金氧半製程下之低漏電電源箝制靜電放電防護電路設計

奈米互補式金氧半製程已被積體電路晶片廣泛地使用，以提升電路的操作速度。然而在先進的製程中，電晶體卻會因閘極穿隧現象 (Gate Tunneling) 而產生嚴重的漏電，尤其在需要大尺寸的電源箝制靜電放電防護電路 (Power-Rail ESD Clamp Circuit) 中更是嚴重。因此，本論文在不調整製程參數的情況下，將電路設計的技巧應用在新型的低漏電電源箝制靜電放電防護電路中，以解決電路漏電的問題。本論文首先於第一章探討穿隧現象的機制，隨著閘極氧化層愈來愈薄，此現象也愈是明顯。在前人的研究中，已建立了穿隧現象的模型和相對應之方程式，本文基於這些研究，應用於接下來的低漏電電路設計之中。第二章提出一種新型的低漏電電源箝制靜電放電防護電，其中利用矽控整流器 (Silicon-Controlled Rectifier, SCR) 作為主要的靜電放電防護元件，並施加低漏電之觸發技術來提昇其靜電放電防護能力。此新型電路利用65奈米互補式金氧半製程模擬，由模擬的結果可發現，此新型的設計可具有相當低的漏電流。第二章提出的新型電路和傳統的電路皆已於同一個65奈米互補式金氧半製程中實作，其晶片量測結果整理於第三章。實驗結果顯示，傳統的電源箝制靜電放電防護電路有著非常嚴重的漏電問題 (室溫下約21.6 µA)，新型的低漏電電源箝制靜電放電防護電路則是只有112 nA的漏電。此外，此新型的電路亦有非常好的靜電放電防護能力，包含人體放電模式(Human-Body-Model, HBM)和機器放電模式(Machine-Model, MM)的靜電放電耐受能力，皆已於本研究中被驗證。

關鍵字

ESD ； LOW LEAKAGE ； IC DESIGN ； POWER-RAIL ESD CLAMP CIRCUIT

並列摘要

The aim of this thesis is to design an ultra-low leakage power-rail ESD clamp in an advanced CMOS technology. The principle is using circuit techniques to reduce the leakage current of the circuit, without undermining the ESD robustness. This thesis is divided in three main parts The first part introduces the evolution of gate-tunneling research. With the gate-oxide thickness become thinner and thinner in CMOS processes, the phenomena become more and more serious. In the past research, the mechanisms and formulas of gate-tunneling have been observed. The model of gate-tunneling also has been applied into advance CMOS processes. In the second part, the proposed solution is presented and the simulation results are shown, using the SPICE models for a 65-nm CMOS process with thin-oxide devices. In the traditional power-rail ESD clamp, the leakage through the MOS capacitor is extremely high. The proposed solution includes a novel design technique to reduce this leakage, and a series of implementations are presented and detailed. In the third part, a test chip is realized and sent to tape-out to realize further analysis. The standby leakage of the circuits is measured, and the ESD robustness is measured by several parameters, such as TLP, turn-on verification, and HMB/MM simulation. The proposed circuits can lead to a leakage current as low as 112nA under 1V-bias at 25°C (opposed to 21.6µA of the traditional power-rail ESD clamp), while the ESD robustness is not changed.

並列關鍵字

ESD ； LOW LEAKAGE ； IC DESIGN ； POWER-RAIL ESD CLAMP CIRCUIT

參考文獻

[1] K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade, “A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 684 – 693, 2004.

[2] A. Annema, B. Nauta, R. Langevelde, and H. Tuinhout, “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 132 – 143, 2005.

[3] M. -D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no.1, pp. 173 – 183, Jan. 1999.

[4] L. Nordheim, “On the kinetic method in the new statistics and its application in the electron theory of conductivity,” Proceedings of the Royal Society of London. Series A, Mathematical and Physical Character, vol. 119, no. 783, pp. 689 – 698, Jul. 1928.

[5] C. A. Mead, “Operation of tunnel-emission devices,” J. Appl. Phys., vol. 32, no. 2, pp. 646 – 652, Apr. 1961.

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奈米互補式金氧半製程下之低漏電電源箝制靜電放電防護電路設計

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