摘要
本篇論文主要探討CMOS製程毫米波頻段放大器的設計方法。在毫米波放大器的設計中，必須著重於主動元件的最佳化與考量傳輸線的分佈效應，而CMOS製程微縮，使主動元件有利於高頻放大器設計；但是晶圓代工廠提供的設計套件，卻缺少適當的傳輸線模型，以致在此頻段的電路設計與最佳化變得非常困難。此外，因為晶片傳輸線的幾何結構與傳統傳輸線不同，所以必須因應此差異而發展新的模型。本文以所建立的傳輸線模型為基礎，討論四個毫米波頻段的CMOS放大器設計，其操作頻率範圍從60 GHz到210 GHz。 第一個電路為低雜訊放大器晶片，設計實現於 0.13微米CMOS 製程。此低雜訊放大器模擬時，使用軟體內建的微帶線模型，此模型經適當的參數調整，可達到足夠的準確性；量測結果顯示，放大器在60 GHz、1.4伏特電壓下消耗10毫安，達到3.8 dB增益、8.5 / 7.0 dB的輸入輸出匹配與6.4 dB雜訊指數，模擬與量測的結果非常接近，表示此模型可以應用在快速的電路模擬中。第二個V-Band低雜訊放大器使用90奈米CMOS製程，匹配電路中的電感性元件，皆由低耗損微帶線架構來實現，此微帶線經由提出的閉合形式積體化微帶線模型最佳化，可提供極佳的耗損特性，因此，在60 GHz、1伏特電壓、消耗5.5毫瓦功率下，此放大器特性可達10.8 dB增益及5.6 dB雜訊指數。第三個電路是使用90奈米CMOS製程W-Band低雜訊放大器，此放大器使用源極電感退化的技術，並對多級串接時，作最佳化推導及設計，在1伏特供應電壓下，僅消耗8毫瓦，在78.5 GHz時，有18 .1dB增益與5.1 dB雜訊指數。 最後一個電路是使用標準40奈米CMOS製程，設計210 GHz放大器，此電路的設計方法，從主動及被動元件出發。在主動元件方面，推導出最大可達成電壓增益公式，用此公式可設計最佳的電路架構，與選擇最好的元件尺寸；在被動元件方面，從推導出的匹配電路耗損，可得知如何減少被動元件耗損。最後應用此兩項分析，協同設計主動與被動元件，而得到最佳的放大器增益。由量測結果可得，本放大器可操作在213.5 GHz，其最大增益為10.5 dB，頻寬為13 GHz，在0.8伏特電壓供應下，直流功率消耗為42.3毫瓦。與已發表的論文比較，此為增益超過10 dB的CMOS放大器中，操作頻率最高的設計。
並列摘要
This dissertation is focused on the design methodology for CMOS millimeter-wave amplifiers. Millimeter-wave amplifier design heavily involves optimization of active devices and consideration of the distributed transmission line effect. CMOS technology scaling greatly benefits in high-frequency amplifier design. However, lacking of appropriate transmission line models in the design kit provided by foundries makes it hard to design and optimize circuits. In addition, as the geometry of on-chip transmission line differs from the modeled one, a novel model was developed to account for the geometric difference. Based on the built transmission line models, four amplifiers were designed in advanced CMOS technologies. Their operation frequencies are in the range from 60 GHz to 210 GHz. The first low-noise amplifier (LNA) was designed and implemented in 0.13 μm CMOS technology. The circuit was simulated by using software built-in microstrip model with two modified parameters. The LNA takes the supply voltage and dc current of 1.4 V and 10 mA. A gain of 3.8dB and an input/output return loss of 8.5/7.0 dB are measured at 60.3 GHz. The simulation results are in good agreement with the measured data, which shows the model is applicable to mm-wave circuit design for quick circuit evaluation. The second V-band LNA has been demonstrated in 90 nm CMOS. Low-loss microstrip lines were designed and optimized by a closed-from expression of the integrated microstrip line to realize all matching networks. Because of the proposed low-loss microstrip lines, the LNA exhibited a low noise figure of 5.6 dB and a gain of 10.8 dB at 60 GHz with only 5.5 mW from a 1.0 V power supply. The third LNA was implemented at W-band in 90 nm CMOS. In the design, the source inductive degeneration technique was used and optimized for multistage cascaded amplifiers. The LNA exhibited a noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1 V power supply. The LNA shows better performance of noise and power with the proposed design principle than the other open literature even with better technologies. The last work presents a 210 GHz amplifier design in 40 nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a hundred GHz amplifier. Accordingly, the bias and the size of transistors, the circuit topology, and the interstage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is 42.3 mW under a 0.8 V supply. To the best of the authors’ knowledge, this chip demonstrates the CMOS amplifier of 10 dB gain with highest operation frequency reported so far.
參考文獻
延伸閱讀
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