適用於低電壓處理器之細細粒度列合併快取記憶體以降低時序差異

A Fine-Grained Line-Mergeable Cache to Reduce Timing Discrepancy with Low Voltage Processors

蔡奇倫(Chi-Lun Tsai)

指導教授 ： 陳添福

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00829

摘要

現今的DVFS處理器系統中，快取記憶體的效能障礙已阻礙系統降低電壓的能力。在低電壓的環境中快取記憶體容易受到製程變異的影響而影響到快取記憶體的延遲與可靠性。可靠性與效能障礙限制了系統操作至更低的電壓。現在已有許多方法被提出來容忍SRAM錯誤以增加可靠性。其中，SRAM depend設計可減緩可靠性障礙與效能障礙，但是這些設計卻提高了快取記憶體的缺失率以及能量開銷。因此，我們注重於減少SRAM延遲而提出一快取記憶體設計。我們提出的快取記憶體同時驅動兩條word-line並且將保持數據相同。此外，我們提出了更細膩的合併策略以減少缺失率以及能量開銷。

關鍵字

低電壓快取記憶體 ； 列合併快取記憶體 ； 降低時序差異

並列摘要

In nowadays DVFS processor systems, caches become a performance barrier of decreasing system voltage. In a low voltage environment, caches that suffer from severe process variation affect the reliability and latency and restrict the system to operate in lower voltage. A number of methods can be used to tolerate SRAM failures to enhance reliability. Moreover, SRAM depend designs can reduce both reliability barrier and performance barrier effect but has miss rate and energy overhead. We propose a cache design focusing on decrease SRAM latency. This cache only triggers two word-lines and writing two word-lines with the same data. Moreover, we propose more fine-grained merge strategies for miss rate and extra write energy overhead decreasing. For decreasing unnecessary energy consumption, our design predicts the last write hit of continuous write and merge lines to improve access time at the moment. Besides, our design selects the occupied line, which has to be discarded the stored data and dedicate the space. With these two data management policy, our design can improve performance by 9% at a cost of 4.5% energy overhead.

並列關鍵字

Low voltage cache ； Line-mergeable cache ； Reduce timing discrepancy

參考文獻

[1] A. Agarwal, B. C. Paul, S. Mukhopadhyay and K. Roy, “Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture,” Solid-State Circuits, IEEE Journal of, vol. 40, no. 9, pp. 1804–1814, 2005.

[2] Q. Chen, H. Mahmoodi, S. Bhunia and K. Roy, “Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS,” in Proc. of the 23rd IEEE Symposium on VLSI Test (VTS), pp. 292–297, 2005.

[3] Gr. Chen, D. Sylvester, D. Blaauw and T. Mudge, “Yield-Driven Near-Threshold SRAM Design,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.18, no. 11, pp.1590–1598, 2010

[6] A. Ansari, S. Gupta, S. Feng, and S. Mahlke, “Zerehcache: Armoring cache architectures in high defect density technologies,” in Proc. of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 100–110, 2009.

[9] M. Mutyam, F. Wang, R. Krishnan, V. Narayanan, M. Kandemir, Y. Xie and M. J. Irwin, “Process-variation-aware adaptive cache architecture and management,” Computers, IEEE Transactions on, vol. 58, no. 7, pp. 865–877, 2009.