利用CMOS-MEMS技術製作低電壓驅動微機械邏輯閘

Using CMOS-MEMS Technology to Fabricate the Low Voltage MEMS Logic Gate

林廷儒(Ting-Ju Lin)

指導教授 ： 陳宗麟

國立交通大學/工學院/機械工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.00971

摘要

本實驗室先前研發微機械邏輯閘（MEMS logic gate），其特點在於可利用單一機械結構實現NAND閘和NOR閘的功能。為了和現有電路進行整合，本研究預計使用CMOS-MEMS製程來製作此一邏輯閘。先前研究受限於製程問題及設計未臻完善，使得製作出的元件存在無法懸浮、無法實現金屬－金屬接觸功能、驅動電壓過高、等問題。本研究針對上述問題，修改後製程與元件設計，提出解決方式。
本研究所使用的製程為TSMC 0.35μm 2P4M，該製程提供的導體層包括：鋁、鎢、雜質參雜的多晶矽、氮化鈦。在研究各材料特性與製程整合可行性後，本研究選用具高熔點、高硬度的氮化鈦來實現低阻抗的接觸（contact）性能規格。然而定義氮化鈦並非2P4M製程的標準步驟，因此如何定義氮化鈦的尺寸與位置，以及如何蝕刻鋁而保留氮化鈦成為本研究的重點之一。
由於必須與現有電路整合以及提高元件的生命週期（life cycles），元件的操作電壓設定在5V以下。元件的操作電壓和元件的剛性及驅動力直接相關。為了避免元件因接觸而產生粘著問題（adhesion problem），元件的剛性不宜設計過低，因此驅動力的估算必須儘可能準確。本元件的驅動力來自於上下電極、0.6μm空隙、1μm二氧化矽所構成的靜電力。傳統的靜電力估算方式直接簡化二氧化矽層所造成的影響，進而造成較保守的靜電力估算。本研究重新推導相關的公式，估算雙層介電材料的靜電力。
本研究藉由量測先前設計／製作的微機電邏輯閘，獲得相關數據，進而重新設計製程與元件尺寸。所完成的新的微機電邏輯閘設計尺寸約250μm x 230μm，共振頻率11kHz，輸入／輸出訊號 （0V, 5V）。目前已完成相關的設計、數值模擬、元件佈局。

關鍵字

邏輯閘 ； 低電壓 ； 氮化鈦 ； 接觸金屬 ； 雙層介電質

並列摘要

In our previous study, we proposed a novel MEMS logic gate that can implement the NOR gate and NAND gate function on the same mechanical structure. In order to promote this MEMS device, this research aims to fabricate the design using foundry-provided CMOS-MEMS process. After experimenting on our first design, we found that the old design suffer from release problem, contact problem, and high actuation voltage problems, and etc. In this research, we proposed a new post-fabrication process and new design, aiming to solve above problems.
The intended CMOS-MES process is TSMC 0.35μm 2P4M, which contains conducting layers including aluminum, tungsten, doped polysilicon, and titanium nitride. After examining the mechanical/ electrical properties and process integrity of each layer, we choose titanium nitride to realize the functionality of low-resistance contact. However, patterning the titanium nitride layer is not a standard service provided by the foundry. Therefore, patterning titanium nitride and etching aluminum while preserving titanium nitride become key issues in this research.
In order to integrate the proposed MEMS device with existing IC circuits and to extend the life cycles of the MEMS device, the MEMS gate should operate below 5Volts. The operating voltage is determined by the actuation force and stiffness of the device. Since the device stiffness cannot be too soft for the sake of adhesion problem, the actuation force should be carefully estimated. In this design, the actuation force comes from the electrostatic force, which involves a 0.6μm air gap and 1μm silicon dioxide between the top and bottom electrodes. The conventional approach neglecting the 1μm silicon dioxide layer results in a conservative estimate of electrostatic force. In this research, we derive the equations for the electrostatic force with composite dielectric materials, to estimate the electrostatic force more precisely.
In this research, we conducted several experiments on the previously designed devices. Using those experimental data, we modified the post-fabrication process and redesign the device dimensions to meet the performance specifications. Currently, the new device has the footprint of 250μm x 230μm, operating voltages (0V, 5V), resonant frequency of 11kHz. The work of performance simulation and design layout has also been completed.

並列關鍵字

logic gate ； low voltage ； TiN ； contact metal ； dual dielectric layers

參考文獻

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