應用時依介電層崩潰理論於電阻式記憶體可靠度與切換機制之研究

此份論文中，我們對電阻式記憶體中的時依介電層崩潰特性做了深入的探討，並將相關知識應用於記憶細胞的長期可靠度預測和電阻切換機制的研究上。首先，在閘極氧化層崩潰的研究領域中，目前已經有相當完善的方法可用於氧化層崩潰的可靠度預測，在此份論文中，我們將這樣的方法用來探討電阻式記憶體細胞中的讀取干擾效應。另外，除了使用以時依介電層崩潰為基礎的預測方法之外，我們也使用了較快速的電壓掃描為基礎的預測方式來做高阻態的讀取干擾生命週期投影，並佐以時依介電層崩潰的實驗結果作為驗證。電壓掃描式的生命週期預測的優點除了提高量測效率之外，其也適用於不同機制的電阻式記憶體中，這結果代表了電壓掃描式的預測成為通用測量方法的可能性。另一部分中，我們將介電層可靠度的相關理論應用於探討電阻切換機制。實驗中，我們在相同的元件測量到兩種不同的電阻切換模式且兩者的介電層崩潰特性有著相當大的差異性，勢必對讀取干擾的可靠度有著相當大的影響。為了深入了解此二切換模式的起因以及特性，我們對其統計特性比如高阻態的時依介電層崩潰、電阻切換特性、電流傳導機制做了全面性的分析與探討。最終我們推論不同的電阻切換模式是源自於電阻切換的位置發生於不同的材質；在二氧化鉿或是介面層之中。此外我們也發現不同的記憶體操作條件會影響電阻切換發生的位置，並進一步影響電阻式記憶體的切換特性。

關鍵字

電阻式記憶體；可靠度；時依性氧化層崩潰

並列摘要

In this thesis, time-dependent dielectric breakdown (TDDB) characteristics of resistive switching random access memory (RRAM) have been thoroughly studied. Several applications have also been demonstrated, such as long-term reliability prediction and understanding on the resistive-switching (RS) mechanism. In the gate dielectric breakdown theory, there are well-established methodologies for lifetime prediction. These methodologies were introduced in this work to study RRAM read disturb immunity. Furthermore, fast TDDB lifetime projection of the high-resistance state (HRS) was performed by ramp-voltage test and verified by the constant voltage TDDB test. Apart from the advantages such as convenience and accuracy, the ramp-voltage-based method was also available in different RRAM cells, indicating its promising potential to become a general methodology to predict read disturb immunity. Additionally, it is also presented that TDDB of HRS is able to provide additional insight into the resistive switching mechanisms. In the same RRAM cell, two RS modes are obtained using different operation schemes. The two RS modes show distinctive electrical and statistical properties. Furthermore, their time-to-SET (tSET) distribution reveals different reliability concerns. Therefore, a comprehensive measurement methodology involving TDDB of the SET process and electrical characteristics of HRS is developed to clarify the origin of the two RS modes, which can be well explained by different locations where RS took place; in bulk high- or interfacial layer (IL) adjacent to silicon substrate. Moreover, changing the operation conditions led to a gradual evolution of the RS location.

並列關鍵字

RRAM ； reliability ； time-dependent dielectric breakdown

參考文獻

[1] "Emerging Research Devices", International Technology Roadmap for Semiconductors, 2011.

[2] R. Waser and M. Aono, "Nanoionics-based resistive switching memories," Nat. Mater., vol. 6, pp. 833-840, 2007.

[3] R. Waser, et al., "Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects, and Challenges," Advanced Mater., vol. 21, pp. 2632-2663, 2009.

[4] H. Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," in VLSI Technology, 2007 IEEE Symposium on, 2007, pp. 14-15.

[5] M. F. Chang et al., "Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC," in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 197-203.

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應用時依介電層崩潰理論於電阻式記憶體可靠度與切換機制之研究

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