應用於LTE之負阻式輸入匹配新穎寬頻低雜訊放大器

A Novel Wide Band Low Noise Amplifier using Negative Resistance Input Matching for LTE Applications

林明道(Ming-Dao Lin)

指導教授 ： 唐震寰

國立交通大學/電機學院/電信工程系所/碩士(2013年)

https://doi.org/10.6842/NCTU.2013.00566

摘要

本篇論文提出了一種結合負阻(Negative Resistance)與共閘極架構應用於LTE系統之新式寬頻低雜訊放大器。研究焦點著重於如何降低低雜訊放大器其功率消耗及雜訊指數，並運用負阻架構來達到輸入阻抗匹配的效果。在以往的低雜訊放大器設計中，一般在輸入端使用RLC回授或是冗長的電感、電容串並聯來實現寬頻匹配電路，而我們的電路使用較少的元件數目來達成寬頻的功能。本電路設計共閘極組態，我們以負阻架構來取代傳統架構中的被動式電感，利用電晶體電流的特性不受頻率影響，作為輸入端之用，並與轉導增強技術達成低功率及有效的降低雜訊，再利用並聯峰值更進一步的壓制高頻雜訊達成很低的雜訊水平。所提出的LNA由TSMC 0.18-μm CMOS製程技術來實現，且藉由CIC的儀器完成量測。
其量測結果如下所述：頻寬為0.5~3.7 GHz，輸入與輸出反射損失皆大於12 dB，最大增益為17.8 dB，最低雜訊指數為3.3 dB，在2.7GHz的P1dB增益壓縮點為-20dBm，IIP3截斷點為-10.3 dBm，核心電路消耗功率為6.48 mW，整體佈局面積包含pad為0.716*0.744=0.533mm2。

關鍵字

長期演進技術 ； 負電阻 ； 互補式金屬氧化物半導體 ； 低雜訊放大器

並列摘要

In this thesis, a novel wide band low noise amplifier combined negative resistance with common gate structure for LTE applications are presented. The research focused on how to reduce the power consumption and noise figure, and using negative resistance to achieve the effect of input impedance matching. In the past, the design of low-noise amplifier used RLC feedback or lengthy inductance, capacitance in series and parallel to achieve broadband matching circuit at the input, however our circuit used fewer of components to increase the bandwidth. In our design, a common gate amplifier with negative resistance using the frequency independent of the transistor current is to replace the traditional architecture of passive inductor at input, and with the gm-boost technique to achieve low power and noise reduction effectively. The shunt peaking network at drain is drawn to further suppress the high-frequency noise and a low noise level is achieved. The proposed LNA is implemented by the TSMC 0.18-μm CMOS technology process, and measured by use of CIC instruments.
The measured results are as follows: bandwidth of 0.5 ~ 3.7 GHz, input and output reflection loss are greater than -12 dB, the maximum power gain is 17.8 dB, the minimum noise figure is 3.3 dB, at 2.7 GHz, the P1dB gain compression point is -20 dBm, the IIP3 cut-off point is -10.3 dBm, the core circuit power consumption is 6.48 mW, and the overall layout area including the pads is 0.716 * 0.744 = 0.533 mm2.

並列關鍵字

long term evolution ； negative resistance ； complimentary metal–oxide–semiconductor ； low noise amplifier

參考文獻

[5] D. K. Shaeffer and T. H. Lee, "A 1.5-V, 1.5-GHz CMOS low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May. 1997.

[6] S. S. Mohan, M. D. M. Hershenson, S. P. Boyd, and T. H. Lee, " Bandwidth extension in CMOS with optimized on-chip inductors," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 346-355, Mar. 2000.

[7] 蔡承修，3-10GHz 寬頻低雜訊放大器，碩士論文，國立中央大學，2008.

[8] A. Bevilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers,” IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 382–383, Feb. 2004.

[9] B. M. Ballweber, R. Gupta, D. J. Allstot, “A Fully Integrated 0.5-5.5-GHz CMOS Distributed Amplifier,” IEEE Transaction on Solid-State Circuits, vol. 35, no. 2, pp. 231-239, Feb. 2000.