應用寫入輔助電路之低功耗雙埠靜態隨機記憶體之測試方法

隨著多核心運算及平行化處理需求漸增，雙埠靜態隨機記憶體在提高效能上的優勢逐漸顯著．另一方面由於記憶體應用層面逐漸由傳統桌上型電腦轉移到行動裝置等相關產品，因此以低功耗操作和高速存取為目標的記憶體設計更是蓬勃發展．然而在先進製程中嚴重製程變異使製造過程中的穩定性相對降低，以及在追求低功耗操作及高速的存取的情況下，雙埠靜態隨機記憶體的的讀取及寫入更加顯得不穩定．上述的不穩定性導致雙埠隨機靜態記憶體在低功耗操作上更顯困難．為了保持可接受的讀取及寫入能力配合降低操作電壓達到低功耗的目的．許多讀取及寫入的輔助電路在各個製程下逐漸被提出使用．本論文著重於討論雙埠靜態隨機記憶體配合寫入輔助電路幫助下之開路缺陷的錯誤行為模式並提出相對應的測試方法．此輔助電路應用於解決雙埠靜態隨機記憶體在先進製程下受到嚴重製程變異使寫入能力衰減嚴重的情況．

關鍵字

雙埠隨機靜態記憶體；測試方法；寫入輔助電路

並列摘要

With the increasing demand of parallel applications and multi-core operations, the advantages of Dual-Port SRAMs have become more important. Also, applications of SRAMs have moved from the traditional desktop to the mobile device; therefore, the designs which are aimed at low-power operations and high-speed accesses are currently prospering. Besides as process variation in the advanced technology becomes more severe, the stability of SRAMs in data retention mode and read/write operation has become more fragile. The low stability property may cause Dual-Port SRAMs unable to operate at low voltage. In order to maintain an acceptable read/write margin with low power issue, some read/write assist circuitries have been proposed recently. As a result, the thesis emphasizes on the fault behaviors of open defects for Dual-Port SRAMs with specific write-assist circuitry and its corresponding test methodologies for those hard-to-detect faults.

並列關鍵字

Dual-Port SRAM ； Test Methodology ； Write Assist Circuitry

參考文獻

[2-1] J.J. Wu, M.F. Chang, S.W. Lu, and et al., ”A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous access Disturbance,” P. 790-794, IEEE Transactions on Circuits and Systems II: Express Briefs, 2012.

[2-2] K. Nii, Y. Tsukamoto, M. Yabuuchi, and et al., ”Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common Row-Access,” P. 977–986, IEEE Journal of Solid-State Circuits, 2009.

[2-3] Y. Ishii, H. Fujiwara, K. Nii, and et al., ”A 28-nm dual-port SRAM macro with active bitline eauqlizing circuitry against write disturb issue,” P. 99-100, IEEE Symposium on VLSI Circuits, 2010.

[2-4] Y. Ishii, H. Fujiwara, T. Doguchi, and et al., “A 28nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues,” P. 2535–2544, IEEE Journal of Solid-State Circuits, 2011.

[2-5] D.P. Wang, H.J. Liao, H. Yamauchi and et al., ”A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage,” IEEE International SOC Conference, 2007.

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應用寫入輔助電路之低功耗雙埠靜態隨機記憶體之測試方法

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