高效能快閃記憶體轉換層設計之研究

快閃記憶體在支援磁碟使用的檔案系統時，需要在快閃記憶體上增加一個快閃記憶體轉換層，提供區塊裝置式介面。因為快閃記憶體有寫入前需抹除的特性，快閃記憶體轉換層使用異地更新及清除流程去回收含廢棄資料的區塊。這些回收的成本是快閃記憶體轉換層效能的關鍵，因為清除流程使用的動作，例如複製頁、抹除區塊等等，都非常耗時。為達高效能的目的，快閃記憶體轉換層應該要最小化清除成本。為了索引邏輯頁的實體頁位置，快閃記憶體轉換層負責維護兩者之間的對映表格。混合式位置轉換快閃記憶體轉換層將快閃記憶體區分為兩個區域，大的資料區域使用邏輯區塊對應實體區塊的管理；小的日誌區域使用邏輯頁對實體頁管理。藉此控制對映資訊的數量，並且達到良好的效能。本論文提出了兩個混合式位置轉換快閃記憶體轉換層。第一個名為ROSE，其中包含了三項用來降低清除成本的新技術。首先，它透過避免連續寫入整個區塊的頁落入不同的區塊，藉此降低回收的成本；同時，不會將隨機寫入、不完全連續寫入，誤判為連續寫入，避免因誤判隨之而來的代價。其次，採用針對混合式位置轉換快閃記憶體轉換層來設計、同時考量區塊的新舊與合併成本的清除方針，藉此提高清除的效率。最後，藉由延遲抹除尚有空白頁的廢棄區塊，並回收使用這些空白頁。第二個快閃記憶體轉換層名為 HybridLog。透過有效率的使用備用區域，HybridLog 在所有的區塊進行日誌式的寫入，有效率的支援新型的 NAND快閃記憶體。日誌式寫入能夠避免寫入無謂的空白資料進入頁，以及降低因為資料區域目標頁已經被寫過、而寫入日誌區域的機率。我們透過模擬評估上述兩個我們所提出的快閃記憶體轉換層的效能。我們使用三個知名的混合式位置轉換快閃記憶體轉換層作為效能比較對象。評估結果顯示，我們所提出的快閃記憶體轉換層的表現優於比較對象。

關鍵字

快閃記憶體；轉換層

並列摘要

A Flash Translation Layer (FTL) provides a block device interface on top of flash memory to support disk-based file systems. Due to the erase-before-write feature of flash memory, an FTL usually performs out-of-place updates and uses a cleaning procedure to reclaim blocks with stale data. The cost of cleaning is a key factor to the performance of an FTL since cleaning involves time-consuming operations such as live page copying and block erasure. To achieve high performance, an FTL should minimize the cleaning cost. To locate each logical page, an FTL manages the mapping (i.e., address translation) between logical page numbers (LPNs) and physical page numbers (PPNs). By dividing the flash memory into two areas, a large data area managed by coarse-grained address translation and a small area managed by fine-grained address translation, a hybrid address translation (HAT)-based FTL can achieve good performance while keeping the size of the mapping information small. In this thesis, two novel HAT-based FTLs are proposed. The first FTL, called ROSE, includes three novel techniques for reducing the cleaning cost. First, it reduces high-cost reclamation by preventing data in an entire-block sequential write from being placed into multiple physical blocks while eliminating the cleaning cost resulting from mispredicting random or semi-sequential writes as sequential ones. Second, it uses a novel cleaning policy that considers both the block age and the cleaning cost in a HAT-based FTL for improving the cleaning efficiency. Third, it delays the erasure of obsolete blocks and reuses their free pages for buffering more writes. The second FTL, called HybridLog, supports modern NAND flash memories by enabling log-style write in all the blocks and efficient use of spare area. The use of log-style write also achieves low cleaning cost by eliminating writes of dummy pages to the data blocks and by reducing the write traffic to the small-sized log area. The performance of the two proposed FTLs is evaluated through simulation. Three well-known HAT-based FTLs are used for performance comparison. The evaluation results show that the two proposed FTLs outperform the HAT-based FTLs.

並列關鍵字

NAND flash ； translation layer

參考文獻

7. Chang, L.P., “Hybrid Solid-State Disks: Combining Heterogeneous NAND Flash in Large SSDs,” in the 13th Asia and South Paciﬁc Design Automation Conference, 2008.

8. Chang, L.P., “On efficient wear-leveling for large-scale ﬂash-memory storage systems,” in the 22st ACM Symposium on Applied Computing, March 2007.

9. Chang, L.P., and Kuo, T.W., “An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems,” in Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium, 2002.

10. Chang, L.P., and Kuo, T.W., “An Efﬁcient Management Scheme for Large-Scale Flash-Memory Storage Systems,” ACM Symposium on Applied Computing, pages 862–868, Mar 2004.

11. Chang, L.P., and Kuo, T.W., “A Real-time Garbage Collection Mechanism for Flash Memory Storage System in Embedded Systems,” in the 8th International Conference on Real-Time Computing Systems and Applications, 2002.

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高效能快閃記憶體轉換層設計之研究

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