The development of analog IC layout generation remains challenges to IC designers due to the imprecise estimation of circuit performance in advanced technology. However, the previous layout results or templates can be reused for the purpose of closing the simulation gap in current analog placement generation. In this work, a practical methodology as well as hierarchical flow is proposed to synthesize layout solutions based on the geometric preservation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we perform replaceable subcircuit-level post-simulation and integrate the simulation factors into the cost function in the layout enumeration strategy. The experiments show that this flow yields valid analog layout results whose performances are near or even better than the layouts implemented by experienced designers or migrated layouts.