使用機器學習技術進行動態電壓與頻率調整測試分級

DVFS Binning Using Machine-Learning Techniques

張耕瑋(Keng-Wei Chang)

指導教授 ： 趙家佐

國立交通大學/電機學院/電子工程系所/碩士(2017年)

摘要

本論文提出一個對晶片進行動態頻率與電壓調整的測試分級架構來避免
冗長的系統測試，其中使用了機器學習技術配合晶圓測試和封裝後測試的結果去做預測，機器學習的核心技術使用了貝氏線性回歸來進行模型擬合，逐步回歸進行特徵選擇。另外，我們也提出了漸進式最大頻率搜尋模型，這個方法可以用來減少收集訓練樣本所需要的時間。實驗總共使用了249個企業提供的系統晶片，可以從實驗結果中看到我們的架構在分級上有很高的正確率，並且不會有將慢速晶片辨認成較快等級的情況發生。在漸進式最大頻率搜尋模型方面，相對於一般的中位數線性搜尋法和二分搜尋法，我們的方法分別節省了45.1%和52.6%的系統測試時間。

關鍵字

動態電壓與頻率調整 ； 速度分級 ； 系統最大操作速度 ； 機器學習

並列摘要

This thesis presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in use are Bayesian linear regression for model fitting and stepwise regression for feature selection. Another method, called the incremental Fmax-model search, is also presented to reduce the test time of collecting the required data for each training sample. The experiments are conducted based on 249 test chips of an industrial SoC. The experimental results demonstrate that our proposed framework can achieve a high accuracy ratio of placing a part into correct DVFS bin without placing any slower part into a faster DVFS bin. The experimental results also demonstrate that the incremental Fmax-model search can save 45.1% and 52.6% of applications of the system-level test compared to the conventional median linear search and binary search, respectively.

並列關鍵字

DVFS ； speed binning ； system Fmax ； machine learning

參考文獻

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