應用於三維可程式邏輯閘陣列之容錯架構探索暨快速重組態演算法

當二維整合電路遇到瓶頸時，三維的製造技術被視為一個很好的解決方案，它是藉由堆疊多個晶粒(die)至單一晶片(chip)並利用直通矽穿孔(through-silicon vias, TSVs)做為垂直方向的連接所完成的。三維的可程式邏輯閘陣列(3D FPGAs)可以被藉由將二維的可程式路由切換器擴展為三維來製作。規律的可程式邏輯閘陣列架構提供了固有不被使用的冗餘元件，這些元件可以被使用於容錯(fault tolerance)的需求，將其視為備用的元件，一旦有任何元件發生故障，則可以利用可程式邏輯閘陣列重新配置(reconfiguration)的功能將故障的元件置換到無故障的備用元件上以達到修復的效果。首先我們針對三維可程式邏輯閘陣列提出了一個考慮到故障元件對於固有冗餘資源需求的重新配置演算法，藉由部分重新配置故障的可程式邏輯單元(CLBs)到無故障的可程式邏輯單元之功能來避免發生故障。實驗結果顯示相較於之前的容錯方法，我們可以提高容錯的修復成功率而且不會有明顯的電路速度衰減。另外針對三維的可程式邏輯閘陣列提出預先佈置冗餘元件的概念進行架構探索，在權衡預先配置與其產生的時間延遲兩項因素下找出具容錯能力較佳的架構。

關鍵字

可程式化邏輯陣列；容錯

並列摘要

Three-dimensional (3D) manufacturing technologies, which stack multiple dies within a single chip and utilize through-silicon vias (TSVs) as vertical connections, are considered as promising solutions to the bottlenecks in 2D integrated circuits. The 3D field programmable gate array (FPGA) can be realized by extending the 2D programmable routing switches to the 3D one. The architectural regularity of FPGAs provides an easy way to allocate inherent redundancy resources (spares), which can be used for fault tolerance. Faulty FPGAs can be repaired by replacing the faulty resources with redundancies. At first, we propose a demand-aware fault-tolerant reconfiguration algorithm for 3D FPGAs that partially remaps the functionality of faulty CLBs to fault-free CLBs to avoid functional faults. Experimental results show that our method can increase the success rate of fault repair without significant timing degradation compared to previous works. Furthermore, we also propose a fault-tolerant pre-allocation concept that performs an architectural exploration for 3D FPGAs, and picks out the most appropriate architectures with a better balance between the success rate of repair and the timing degradation.

並列關鍵字

FPGA ； Fault tolerant

參考文獻

[1] International Technology Roadmap for Semiconductor. Semiconductor Industry Association 2005–2010.

[2] A. W. Topol, D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM J. of Res. and Develop., vol. 50, no. 4/5, pp. 491–506, Jul.–Sep. 2006.

[3] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep submicron interconnect performance and systems-on-chip integration,” Proc. IEEE, vol. 89, no. 5, pp. 602–633, May. 2001.

[4] R. R. Tummala and V. K. Madisetti, “System on chip or system on package?” Design & Test Computers, vol. 16, no. 2, pp. 48–56, Apr.–Jun. 1999.

[6] K. L. Tai, “System-In-Package (SIP): challenges and opportunities,” Asia South Pacific Design Automation Conf., pp. 191–196, 2000.

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應用於三維可程式邏輯閘陣列之容錯架構探索暨快速重組態演算法

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