高壓半導體元件淺溝槽隔離製程之差排改善及良率提昇研究

Dislocation Improvement and Yield Enhancement for the Process of the Shallow Trench Isolation of High Voltage Semiconductor Devices

嚴永民(Yung-Ming Yen)

指導教授 ： 潘扶民

國立交通大學/工學院/工學院半導體材料與製程設備學程/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.01155

摘要

隨著半導體製程技術進步，元件越做越小，互補式金氧半高壓(High Voltage Complementary Metal-Oxide-Semiconductor, HV CMOS)元件製程技術要求也更加精確，在小線寬及高積極度的要求下，元件間干擾越來越明顯，被用來作為元件之間絕緣的淺溝槽隔離製程(Shallow Trench Isolation, STI)也就變得愈來愈重要。
然而，淺溝槽隔離技術有許多問題尚需解決，應力之問題是一個重要研究方向。應力會造成如差排(Dislocation)這類的缺陷，會影響元件之基本電子特性降低可靠度。一般產生較大應力的來源可能有幾種：一種為平坦化製程產生之應力，即化學機械研磨淺溝槽回填二氧化矽時所產生。或是銅製程之鑲嵌技術(Damascene)，使用化學機械研磨(Chemical Mechanical Polishing, CMP)之技術，所造成之機械應力。第二種即熱製程所產生之應力，就是由於矽底材和所回填的二氧化矽的熱膨脹係數不同所引起之應力。這應力會造成晶格位置的差排，而產生有不正常之漏電流行為。尤其在ULSI的世代以後，元件之主動區(Active Area)面積更加為縮小，淺溝槽隔離技術下應力所產生問題更為嚴重，更增加元件微縮的挑戰。本研究即主要探討熱製程(Thermal Cycling)所產生的應力成因，並優化內墊氧化矽層(Liner Oxide)與內墊氮化矽層(Liner Nitride)之溫度及厚度，以減少差排的產生。

關鍵字

互補式金氧半高壓 ； 內墊氧化矽層 ； 內墊氮化矽層

並列摘要

Shallow Trench Isolation (STI) techniques are essential for semiconductor device for reducing electrical interferences between devices of sub-micro and sub 100-nm High Voltage Complementary Metal-Oxide- Semiconductor. By separating active regions with oxide isolation structures, it is possible to reduce the cross-talk between elements. STI has become more and more important as the dimension of devices continuously scales down.
However, the mismatch in thermal and mechanical properties between the oxide and the silicon substrate create, enormous stress and results in current leakage due to the generation of dislocations in active zones. As a result, it is important to carefully design the isolation structures. In the STI structure, a significant stress is built up in the silicon mesa during the thermal cycling process after the STI formation. The thermal cycling lead to tensile stress as a result of the difference in the thermal expansion coefficient between the silicon substrate and the trench fill oxide. As the active area pitch decreases, an increase both in the stress and the leakage current density is observed. The stress causes a large amount of defects, which results in a large leakage current density. This study explores the cause of the cause of the stress build-up during thermal cycling process. We optimize the thickness of the liner oxide layer and the liner nitride layer and the thermal cycling temperature to eliminate the production of the dislocation.

並列關鍵字

HV CMOS ； Liner Oxide ； Liner Nitride

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