28奈米高介電係數金屬閘極4kb先進先出記憶體

能低電壓操作的低功率嵌入式記憶體近年來逐漸成為晶片系統領域的研發重心，用以降低晶片系統整體的動靜態功耗，也藉此能應用在可攜帶式的手持攜帶或低功率生醫感測等裝置上。　　首先，根據研究次臨界電壓元件功耗特性曲線，本論文提出一個漣波位元線架構，以及負壓位元線寫入強化電路設計，來實現一個使用聯電二十八奈米高介電係數金屬閘極製程的四千位元次臨界低功率先進先出記憶體晶片，將整體讀寫操作電壓同時降低到低於元件閘電壓的最低可操作電壓。與傳統的階層式位元線架構相比，該設計大幅改善了記憶體電路在低電壓下的操作速度、功耗以及節省所需要的金屬層數。　　此論文提出的９Ｔ先進先出記憶體組成的４ｋｂ晶片面積是１６９ｘ１８５平方微米；該晶片具有能在低電壓下操作的電壓範圍，測試正常操作電壓為０.９伏特到０.４伏特；在典型製程、攝氏２５度和０.９伏特的工作環境下，最大的工作頻率為１.１ＧＨｚ。

關鍵字

低電壓操作；先進先出記憶體；漣波位元線架構；負壓位元線寫入強化電路設計

並列摘要

Nowadays, the embedded memory operating in low voltage progressively becomes a major trend in System-On-Chip (SoCs) to reduce the dynamic and standby power for portable devices and for ultra-low power bio-medical and wireless sensor applications. This thesis presents a novel two-port disturb-free 9T SRAM-based FIFO with ripple read bit-line (RBL) and negative write bit-line (WBL) write assist structure to enhance subthreshold operation. As the process scales down, the wire delay little by little dominates the whole delay, especially for the subthreshold region. The proposed Ripple bit-line structure divide the bit-line into several segments by the ripple buffer. Therefore, the wire delay can be reduced apparently. Furthermore, due to the programmable property of FIFO, the Ripple bit-line structure can reduce the power consumption efficiently. The proposed 9T SRAM cell has independent single-ended RBL and WBL and bit-interleaving architecture for enhanced soft error immunity. A 4kb test chip is implemented in UMC 28-nm high-k metal gate (HKMG) CMOS technology. Measured full functionality is error-free from 0.9V down to 0.4V. The measured maximum operation frequency at 0.9V , tt corner and 25℃ is 1.1GHz..

並列關鍵字

low voltage ； FIFO ； ripple bit-line structure ； negative bit-line write-assist

參考文獻

[4]. EVERT SEEVINCK, FRANS J. LIST, and JAN LOHSTROH, "Static-Noise Margin Analysis of MOS SRAM Cells", IEEE J. Solid-State Circuit, VOL. SC-22, NO. 5, OCTOBER 1987.

[5]. T. Fischer, E. Amirante, P. Huber, T. Nirschl, A. Olbrich, M. Ostermayr, and D. Schmitt-Landsiedel, “Analysis of read current and write trip voltage variability from a 1-mb sram test structure,” IEEE Trans on Semiconductor Manufacturing, 2008, vol. 21, no.4, pp. 534–541.

[7]. Sridhar Ramalingam, Elakkumanan Praveen, Natarajan Sreedhar, "Tutorial 6: Design Challenges and Solutions for Nanoscale Memories", IEEE International Symposium on Circuits and Systems, 2007, nil28-nil29.

[9]. Chi-Shin Chang et al., "A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist," Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.1468,1471, 19-23 May 2013

[10]. Chien-Yu Lu et al., "A 0.33-V, 500-kHz, 3.94- 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.59, no.12, pp.863,867, Dec. 2012

國際替代計量

28奈米高介電係數金屬閘極4kb先進先出記憶體

全文下載

主題瀏覽