共接放電之失真波形導致機械模式靜電防護失效探討

ESD Machine Model Failures Caused by The Distorted Waveforms During Multiple-pin Zapping

陳奕安(Yi-An Chen)

指導教授 ： 潘扶民

國立交通大學/工學院/工學院半導體材料與製程設備學程/碩士(2013年)

https://doi.org/10.6842/NCTU.2013.00730

摘要

電子元件的靜電防護能力，需要在產品設計後加以實際驗證，會根據JEDEC協會所定義的項目及方法來執行，其中最廣泛被接受的是MM mode，藉由測詴機台給予相對應的符合規範的模擬條件，包含電流強度，電壓大小，振盪週期，以及電子元件的腳位的分類組合，皆須符合測詴規範 本論文將要揭露一種來至於機台所造成衰減MM mode抵抗強度的機制。此種使得MM mode評估降等的現象，推斷是來自進行MM mode測詴時，因為MM脈衝同一時間對並聯的多根接腳進行放電，導致機台電感減少，MM mode峰值電流因此而增加，進而增加傷害的程度。並且提出一個用以解釋波形變形失真原因的理論模型，此一模型乃經過SPICE模擬驗證。

關鍵字

靜電防護 ； 機械模式

並列摘要

Static protection design of electronic components need to be verified in actual product, and should be performed under the project and methods defined by JEDEC association. MM mode is one of the most widely accepted method. The test machine provides corresponding simulation conditions the are subject to the test specifications, including amperage, voltage magnitude, oscillation period, as well as clusters of component‘s pins.
This paper presents a tester-induced MM downgrade mechanism. The MM downgrade phenomenon is suggested to arise from the enhanced MM peak current which is caused by the reduced inductance in the MM tester as the MM pulse is zapped to multiple pins. A model verified by SPICE simulation is proposed to explain the waveform distortion.

並列關鍵字

ESD ； machine model ； waveform ； JEDEC ； SPICE

參考文獻

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