基於記憶體式乘法器並實現於可程式邏輯閘陣列之高速且面積最小化的有限脈衝響應濾波器設計

High-Speed and Area-Minimized FIR Filter Design using Memory-Based Multiplication on FPGAs

許晉維(Jin-Wei Hsu)

指導教授 ： 黃俊達

國立交通大學/電機學院/電子工程系所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00122

摘要

在有限脈衝響應濾波器中最複雜的部份為多重常數乘法器(MCM)區塊，它將一筆資料乘上多個常數係數。而多重常數乘法器區塊中的乘法器可利用基於記憶體架構的乘法器來取代，因此為了減少記憶體大小有許多方法被提出來。在此篇論文中，我們提出一個以整數線性規劃(ILP)為基礎的方法，藉由尋找最少數目的共用部份乘積來實現所有的常數乘法，最小化多重常數乘法器區塊面積，並將其運用於現場可程式化邏輯閘陣列。由實驗結果可知，我們的方法和文獻上所知最先進的作法相比，以平均值而言，減少了超過10%的延遲和50%的面積，且當常數係數個數增加時記憶體大小減少的幅度更為明顯。

關鍵字

有限脈衝響應濾波器 ； 記憶體式乘法器 ； 可程式邏輯閘陣列

並列摘要

The complexity of finite impulse response (FIR) filters is dominated by multiple constant multiplication (MCM) block which realizes the multiplication of one data sample with multiple constant coefficients. Many works have been proposed for minimizing memory size since multiplications in an MCM block can be implemented by memory-based multipliers. In this work, we present an integer linear programming (ILP) based approach to minimize the area of MCM block implemented on the field programmable gate array (FPGA) by finding the minimal number of common partial products to carry out all constant multiplications. Experimental results show that on average, compared with an existing state-of-the-art method, the proposed method reduces delay and area by more than 10% and 50%, respectively. Moreover, the reduction of memory size is more prominent when the number of constant coefficients increases.

並列關鍵字

FIR filter ； Memory-Based Multiplication ； FPGA

參考文獻

[1] H.-R. Lee, C.-W. Jen, and C.-M. Liu, “On the design automation of the memory-based VLSI architectures for FIR filters,” IEEE Trans. Consum. Electron., vol. 39, no. 3, pp. 619–629, Aug. 1993.

[4] D. F. Chiper, “A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine and sine transforms,” in IEEE Conf. Image Process., Oct. 1999, pp. 764–768.

[5] D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraits, “Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1125–1137, Jun. 2005.

[6] P. K. Meher and M. N. S. Swamy, “New systolic algorithm and array architecture for prime-length discrete sine transform,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 3, pp. 262–266, Mar. 2007.

[7] P. K. Meher, J. C. Patra, and M. N. S. Swamy, “High-throughput memory-based architecture for DHT using a new convolutional formulation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 606–610, Jul. 2007.