基於RISC-V SoC的Virtual Memory設計與實作

The Design and Implementation of Virtual Memory for A RISCV-V CPU

李沿槱(Yen-Yu Lee)

指導教授 ： 蔡淳仁

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2020年)

摘要

本論文的目的是為一個基於RISC-V指令集架構的開源碼處理器Aquila設計一個虛擬記憶體管理單元 (MMU)。Aquila支援RV32IMA指令集，也可以執行不需要MMU的即時作業系統核心。
然而，許多作業系統，包含了Linux，都有著支援虛擬記憶體的需求。由於Linux是最廣為採用的嵌入式作業系統之一，因此，在本論文中，我將為Aquila設計實作一個虛擬記憶體管理單元。並在實作完成後，我們會利用RISC-V官方的測試資料，配合Verilator模擬器來驗證我們所實作的Aquila加上MMU的RTL模型可以正確執行虛擬記憶體管理。此外，我們也使用Xilinx FPGA 開發板合成並測試整個系統，並與另一個開源RISC-V處理器Ariane做效能比較及分析。

關鍵字

記憶體管理單元 ； 虛擬記憶體

並列摘要

The goal of this research is to design a memory management unit (MMU) for an open-source processor, Aquila, based on the RISC-V instruction set architecture Aquila supports RV32IMA instruction set and is capable of running real-time OS kernels that does not require MMU.
However, many operating systems, including Linux, require virtual memory support. Since Linux is one of the most popular operating systems for embedded systems, therefore, in this research, we will design and implementation an MMU to enable virtual memory support for Aquila. The RISC-V official ISA test cases are used to verify the correctness of the proposed RTL model using the Verilator simulator. The design is also synthesized and verified on a Xilinx FPGA development board. Moreover, the performance of the proposed design will be compared against another open-source RISC-V CPU, Ariane.

並列關鍵字

RISC-V ； MMU ； Virtual Memory

參考文獻

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[6] M. Cekleov and M. Dubois, "Virtual-address caches.2. Multiprocessor issues, " in IEEE Micro, vol. 17, no. 6, pp. 69-74, Nov.-Dec. 1997, doi: 10.1109/40.641599.

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[1] 巫謹佑，「基於RISC-V指令集架構的SoC之設計與實作」，國立交通大學，碩士論文，民國108年。

[2] ETH Zurich, PULP Platform Project.[Online] Available: https://pulp-platform.org/