大面積石墨烯薄膜的製備及其電晶體電學性質之研究

石墨烯是一種二維材料，由單層的碳原子以蜂巢狀排列而成之結構，具有良好導熱性、電子遷移率、穩定的化學特性和高穿透率。製備方式由最初的機械剝離法演化至碳化矽磊晶、氧化還原和常見的化學氣相沉積法，其石墨烯的尺寸也從局部區域擴展至大面積。一開始本論文成長石墨烯的方式是以高溫熱裂解的化學氣相沉積法作討論，與傳統 CVD 成長石墨烯的差異是改用固態碳源 PMMA 取代甲烷或乙炔等的碳氫化合物氣體，我們發現在金屬薄膜與 SiO2 基板間形成一石墨烯薄膜，而針對此薄膜，我們改變各種成長參數如降溫速率、成長溫度和金屬催化劑厚度來討論薄膜品質的優劣。經快速降溫析出的石墨烯較完整且品質較好；較高的成長溫度薄膜品質也較佳；太薄或太厚的金屬催化劑也容易形成缺陷較高的薄膜。藉由直接成長於氧化矽基板上的高品質石墨烯，對往後的元件製作和其電性量測研究是相對於方便的。除了石墨烯薄膜的製備外，本論文亦針對石墨烯的電學特性作討論，利用不同溫度成長的石墨烯製備成電晶體元件，並由閘極場效應量測得知高品質的石墨烯表現的電流調制現象較明顯；預期藉由電流熱退火方式去除由大氣中水氣造成的 p 型摻雜；最後我們嘗試由部份覆蓋的頂閘極元件來創造在石墨烯中載子濃度的不同分佈，由其結果顯示我們並無法得到類似 PN 接面的電流電壓特性。

關鍵字

石墨烯；化學氣相沉積法；電晶體元件；閘極場效應；電流熱退火

並列摘要

Graphene, a single atomic layer of carbon constructed in a two dimensional structure has a high thermal conductivity, excellent electron mobility, stable chemical ability and high transmittance. The approaches of preparing graphene have been developed from exfoliation method to SiC sublimation, oxide reduction and chemical vapor deposition. The size of graphene change from only few micro-meter to wafer size as well. Due to the precipitation mechanism of carbon atoms from the Ni template, soild carbon source is applied to fabricate graphene film on Ni template with thermal CVD at the beginning of this thesis. For the graphene formed between Ni templates and SiO2 substrates, different growth conditions including cooling speed, growth temperature and metal template thickness are discussed. With fast cooling speed, the segregation process of carbon atoms becomes more complete and lead to better graphene quality. At higher temperatures, better quality graphene can be obtained. At thinner and thicker Ni thickness, obviously metal desorption and poor carbon atoms segregation process are observed, respectively. With the fabricating of high quality underneath graphene, device of graphene can be easily approached. Graphene film fabricated with different growth temperature is applied on the back gate transistor device. With higher growth temperature, current modulation becomes more obvious due to better graphene quality. Current annealing process is applied on the same device in order to eliminate heavy p-type doping on the graphene film because of chemical solution and water in the air. At last, a partially capping top-gate graphene transistor is fabricated. The symmetric current-voltage characteristics reveal that even different carrier concentrations are experienced in the graphene stripe, no PN junction like behavior is observed for the device.

並列關鍵字

Graphene ； CVD ； transistor device ； gate field effect ； current annealing

參考文獻

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大面積石墨烯薄膜的製備及其電晶體電學性質之研究

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