嵌入式影像處理系統及 SURF 特徵擷取

Embedded Image Processing System and SURF Feature Extraction

徐尉嘉(Wei-Jia Hsu)

指導教授 ： 宋開泰

國立交通大學/電機學院/電機學院電機與控制學程/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00669

摘要

本論文主要目的在研製一個嵌入式影像處理卡，未來能將其應用在機器人上進行特徵擷取及各種的影像處理演算法。本影像處理卡之電路設計可以分成數位訊號處理器(DSP)及可程式邏輯閘陣列(FPGA)兩個模組。影像擷取採用低功耗及小尺寸的CMOS影像感測器，其輸出格式設定為YUV4:2:2，擷取的影像尺寸則是512x480像素。DSP採用德州儀器公司的TMS320C6414TGLZ7，主要用於實現影像處理演算法；FPGA採用 Altera公司的EP2C35F672C6 ，用於比較低階的影像處理及CMOS影像感測器控制。本論文成功地於所研製的影像處理卡中實現加速強健特徵(SURF)演算法，透過USB介面將所擷取的影像畫面及SURF描述子傳送到個人電腦顯示及進行特徵匹配。實驗結果顯示，即時影像擷取週期大約33.5ms；當SURF描述子數量等於64個，計算時間大約417.5ms；當SURF描述子數量為199個，計算時間大約是985ms；依樣本模型在特徵擷取時設定的門檻值不同，特徵匹配率則由70.2%變化到20%。

關鍵字

數位訊號處理器 ； 可程式邏輯閘陣列 ； 加速強健特徵 ； 嵌入式

並列摘要

This thesis aims to develop an embedded image processing board, which can be used to realize various image feature extraction and processing algorithms for robotic applications. The circuitry of this image board can be divided into two parts, one is for a digital signal processor (DSP) and the other for a field programmable gate array (FPGA). A low power, small size CMOS image sensor with YUV4:2:2 image format and 512x480 pixel size is adopted for image acquisition. The DSP module is mainly used for implementing image processing algorithms, while the FPGA module for lower level image processing and sensor control functions. In this work, the TMS320C6414TGLZ7 DSP from Texas Instruments Corporation and the EP2C35F672C6 FPGA from Altera Corporation were selected for the image board. In this work, speeded-up robust features (SURF) algorithm has been successfully realized on the developed image board. An USB interface with average throughput of 22MB/sec works to transfer acquired image frames and extracted SURF descriptors to a personal computer, where feature matching is executed. Experimental results show that the refresh period of frame grabbing is about 33.5ms. When the number of SURF descriptor is equal to 64, the computing time is about 417.5ms; when the number of SURF descriptor is equal to 199, the computing time is about 985ms. The typical matching rate varies from 70.2% to 20%, depending on the threshold of the patterns used in feature extraction.

並列關鍵字

DSP ； FPGA ； SURF ； Embedded

參考文獻

[1] Herbert Bay, Andreas Ess, Tinne Tuytelaars and Luc Van Gool, "SURF: Speeded Up Robust Features," Computer Vision and Image Understanding , Vol.110, No.3, 2008, pp.346-359.

[3] Stephanie McBader and Peter Lee, "An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems," in Proceedings of the International Parallel and Distributed Processing Symposium, Nice, France, 2003, pp.228-232.

[5] P. Chalimbaud and F. Berry, "Design of an Imaging System based on FPGA Technology and CMOS Imager," in Proceedings of IEEE International Conference on Field-Programmable Technology, Brisbane-Australia, 2004, pp407-411.

[6] Stefan Mahlknecht, Roland Oberhammer and Gregor Novak, "A Real-time Image Recognition System for Tiny Autonomous Mobile Robots," in Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium, Toronto, Canada, 2004, pp.324-330.

[7] Fen Xu, Jian-Jun Zeng and Yun-Long Zhang, "Design of a DSP-based CMOS Imaging System for Embedded Computer Vision," in Proceedings of IEEE Conference on Cybernetics and Intelligent Systems, Chengdu, China, 2008, pp430-433.