使用氧化薄化奈米尺度片狀通道之具PI型閘極無接面薄膜電晶體之製作與特性

近年來，無接面薄膜電晶體(JL TFTs)的各種研究成果陸續被發表在各大期刊，其對於三維元件的整合有高度的幫助。JL TFTs 其通道為高摻雜濃度的同型載子，由於源極、汲極以及通到的摻雜是相同的，因此稱為無接面電晶體。JL TFTs 可應用於各種元件，如一般電晶體、記憶體、可變電阻......等。JL TFTs 的結構相對簡單，因此其在嵌入式三維元件的製造中佔有較大的優勢。有鑑於以後的三維平面式元件無法全部都用單晶矽還製作，因此多晶矽電晶體的研究是必然的。多晶矽的特性會隨著結晶粒的大小而有所改變，晶粒越大的薄膜電晶體會擁有趨向於單晶矽電晶體的特性。本篇論文的研究內容就是針對多晶矽無接面薄膜電晶體的各種特性與製作，其中包含電晶體導通的機制與理論、電流-電壓特性、高溫的影響、氨電漿的影響，以及雜訊分析。機制的部份會搭配上ISE TCAD模擬來輔助說明。製作的方法則是利用氧化薄化的方式使結晶的顆粒達到近似單晶的程度，藉此改善JL TFTs 的電性。根據我們的研究，使用氧化薄化做出來的奈米尺度片狀通道之具PI型閘極JL TFTs 擁有類單晶的晶向。從電性的結果來說，此方法所做出來的元件擁有較好的電性，較小的subthreshold slop，並且幾乎沒有GIDL、DIBL、kink effect等效應。另一方面，從溫度效應、氨電漿前後的缺陷分析、以及flicker noise的雜訊分析，從這些都可以得出近似單晶才會有的特性。由此我們可以說，利用氧化薄化的方法可以做出近似單晶的特性，無論是從TEM上的結果，還是電性分析上的結果，我們都可以得出此結論。此研究成果將有可能對於三維元件的開發上有莫大的幫助。

關鍵字

PI型閘極；無接面薄膜電晶體

並列摘要

Recently, investigations of junctionless (JL) thin film transistors (TFTs) have been published in electrical journals. Junctionless MOSFET devices with high doping concentration within the channel and source/drain regions has been proposed to eliminate the junction related performance degradations for future nano-device application. Such a feature has also been demonstrated with poly-Si TFTs which is very suitable for embedding into an entire electronics system on panel (SOP) as device performance improves further and for high-density 3D stacked applications. Another benefit is that the fabrication flows of JL TFTs are simple and fit for embedded process such as embedded flash memory. The characteristics of JL MOSFETs have been demonstrated in silicon on insulator (SOI) wafer. Furthermore, the ultra-thin channel is requirement, which cause the fabrication in a high degree of difficulty. However, poly-Si thin-film transistor (TFT) has subsequently been introduced for high packing density and low of the interconnection delay, power consumption and cost. Owing to the characteristics of JL TFTs such as ON-state current and effective mobility are dominated by the thickness itself and the grain size of poly-Si channel. In our works, this study investigates the poly-Si channel of JL TFTs with large grain size, giving consideration to the excellent switch performance. The electrical performance and temperature dependence of parameters for the JL-TFT device are also addressed. Furthermore, the NH3 plasma treatment could further improve the performance, and using the flicker noise to analyze the channel defect of the device. The mechanisms of JL devices have been demonstrated in this paper with devices simulation and semiconductor theory, and illustrated the measurement result with ISE TCAD simulation. In result, the single crystal-like channel in the nano-sheet channel layer is obtained from the TEM images, temperature dependence, flicker noise analysis and the result of NH3 treatment. A steeper subthreshold slop is exhibited and the effects of GIDL, DIBL, and kink effect are resisted in the structure of JL TFTs. This investigation explores its potential in future TFT for a system on panel and high-density 3D stacked applications.

並列關鍵字

junctionless ； PI gate ； oxidation thinning ； Nano-sheet Channel

參考文獻

Chapter 1

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[1-10] H. C. Lin, C. I. Lin, T. Y. Huang, “Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors with an Ultrathin Channel,” IEEE Electron DeviceLett.,vol. 33, pp. 53–55, Jan. 2012.

[1-11] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, H. M. Choi, K. Hwang, Y. Ko, and C. J. Kang, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash,” in Proc. IRPS, 2011.

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使用氧化薄化奈米尺度片狀通道之具PI型閘極無接面薄膜電晶體之製作與特性

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