具獨立雙閘極之N型無接面奈米線電晶體的製作與特性分析

在本篇論文中，我們成功製作出具獨立操作雙閘極之n型無接面多晶矽奈米線電晶體。此元件在通道中擁有高摻雜濃度，且由於具有極小的奈米線尺寸，因此閘極可以有效地控制並開關元件。另外，此種元件的電性表現，包含基本特性以及次臨界特性，都將與操作在傳統模式(inversion mode, IM)下，具有無摻雜通道的傳統元件做個比較。在整個多晶矽通道導通的情況下， J-less元件明顯具有較IM元件大的電流驅動力。此外，在兩個獨立閘極所提供多元操作的彈性下，我們將這兩種元件間不同的傳導機制成功地做區隔，並利用TCAD的模擬結果來做驗證。其次，由於J-less元件所提供的表面空乏區使得等效閘極介電層厚度的增加，因此具有較差的短通道效應。此外，在單閘極操作模式下，由於J-less元件所提供的表面空乏區使得等效閘極氧化層厚度相較於雙閘極操作模式下為厚，而導致其擁有較差的閘極控制能力以及較負的臨界電壓。另一方面，在通道的摻雜濃度愈高的情況下，J-less元件會愈來愈難有效開關；更甚者，當通道的摻雜濃度愈來愈高時，會使得J-less元件有愈來愈惡化的短通道效應以及較為敏感的臨界電壓變化。同時，利用TCAD模擬軟體，我們可以推論具有較低通道摻雜濃度的J-less元件將會有效地隨著不同的閘極驅動力而調整其空乏區，故而擁有較佳的閘極控制能力。然而，在通道的摻雜濃度足夠高的前提下，J-less元件在臨界電壓的表現上會有相對於傳統IM元件完全相反的趨勢。

關鍵字

獨立雙閘極；無接面奈米線電晶體；導通機制； TCAD模擬；閘極控制能力；短通道效應

並列摘要

In this thesis, we have successfully fabricated n-type juntionless (J-less) independent double-gated (IDG) poly-Si nanowire (NW) transistors which have highly doped channels but can be effectively turned off on account of the ultra-thin feature size of NWs. In addition, the electrical characteristics are well compared to the conventional devices with undoped channels which operate in the inversion mode (IM). Owing to the fact that the current conduction is through the whole Si channel, the Ion characteristics are obviously better for the J-less devices, so do the output characteristics. Moreover, due to the flexibility in device operation offered by the two independent gates, the differences of conduction mechanisms between the two types of devices can be clarified and confirmed by the TCAD simulation results. We also found that short channel effects (SCEs) are more severe for the J-less devices, which is ascribed to the additional equivalent oxide thickness (EOT) contributed by the surface depletion layer. Also, the J-less devices have poorer gate controllability under the SG mode owing to the thicker EOT, resulting in the more negative Vth over that of the DG mode. On the other hand, the higher channel doping concentration the J-less devices have, the harder the J-less devices can be effectively turned off at Vg = 0. Moreover, as the channel doping concentration is higher, the SCE for the J-less devices gets much worse, and the Vth of the device becomes more sensitive to the channel doping. Also, utilizing the TCAD simulation, we can extrapolate that the J-less devices with lower channel doping concentration possess better gate controllability since they can more effectively modulate the depletion region with varying gate overdrive. Finally, as the channel doping is sufficiently high, the J-less devices show Vth characteristics (DG > SG-2 >SG-1) opposite to those observed for the IM devices.

並列關鍵字

independent double-gated ； juntionless nanowire transistors ； conduction mechanism ； TCAD simulation ； gate controllability ； short channel effects (SCEs)

參考文獻

[23] J. P. Wu, “Fabrication and Characterization of P-Type Accumulation-Mode Independent Double-Gated Poly-Si Nanowire Transistors”, Master thesis, Institute of Electronics, National Chiao Tung University, p. 49, Mar. 2011.

[1] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE, vol. 89, no. 3, pp. 259–288, Mar. 2001.

“Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, p. 053511, 2009.

[3] A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” Proc. Euro. Solid-State Device Res. Conf. (ESSDERC), 2010, pp. 357–360.

[4] C. Y. Chen, J. T. Lin, M. H. Chiang, and K. Kim, “High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application,” Proc. SOI Conf., 2010, pp. 1–2.

國際替代計量

具獨立雙閘極之N型無接面奈米線電晶體的製作與特性分析

全文下載

主題瀏覽