寬廣量測範圍與高解析度以循環游標尺式為基礎之時間至數位轉換器

A Wide Range and High Resolution Cyclic Vernier Based Time-to-Digital Converter Using a Time Amplifier

黃詩晏(Shih-Yen Huang)

指導教授 ： 許騰尹

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00980

摘要

時間至數位轉換器廣泛被應用在精密時間量測儀器和鎖相迴路。如何設計一個寬廣量測範圍、高解析度的時間至數位轉換器是本論文的設計重點。本篇論文所提出的時間至數位轉換器採用計數器法得到193ns的輸入量測區間以及使用時間放大法改善循環游標尺時間至數位轉換器的解析度至2.6 ps。為了更細的解析度需求，一個0.1 ps死區和高敏感度的相位偵測器被提出用來觀測的粗調和細調數位控制振盪器的相位差紀錄。
所有的數位至時間轉換器的電路部件是以台積電65nm 1P6M標準元件庫實現以及
以電子設計自動化工具完成布局和繞線。整個核心面積為0.05 mm2 和整體功率消耗在1V供應電壓下為2.57 mA。

關鍵字

時間至數位轉換器 ； 時間放大器 ； 游標尺 ； 全數位鎖相迴路 ； 相位偵測器

並列摘要

Time-to-digital converter (TDC) is widely used in precise time measurement equipment and PLLs. How to produce a wide input range and high resolution TDC is an important design issues in this paper. The proposed TDC adopts the counter method to gain 193ns input measurement range and it uses time amplification method to improve Cyclic Vernier TDC resolution to be 2.6 ps. For fine resolution requirement, a 0.1ps dead zone phase detector is proposed to monitor the history of the phase difference between coarse and fine DCOs.
All circuits in the TDC are implemented by the TSMC 65nm 1P6M standard cell library and placed and routed by automatic EDA tools. The core area is 0.05 mm2 and the power consumption is 2.57 mW with 1 V supply voltage.

並列關鍵字

Time-to-digital Converter ； Time Amplifier ； Vernier ； TDC ； All-Digital Phase-Locked Loop ； Phase Detector

參考文獻

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