金氧半製程之次兆赫茲接收機型式鎖相迴路電路設計

DESIGN OF SUB-THZ RECEIVER-BASED PHASE-LOCKED LOOP IN CMOS TECHNOLOGY

王艶婷(Yan-Ting Wang)

指導教授 ： 陳巍仁

國立交通大學/電機學院/電子工程系所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.01029

摘要

依據MIT 2004 年之技術評鑑報告，兆赫茲電磁波(300GHz~3THz)為非離子化輻射波，相較於X-射線對人體之風險較低，是公認理想之醫學影像信號源。除此之外，兆赫茲電磁波對於分子檢測、金屬探測、安檢系統、短距離雷達及超高速無線資料安全傳輸等應用，亦深具潛力，為近年來科學及工程上之重點研究領域。
過去兆赫茲信號源多採用高功率雷射結合光學模組及化合物半導體實現，其體積及成本耗費甚巨，普及化有其困難。隨著互補式金屬氧化物半導體製程技術之演進，電晶體之功率單位增益頻率已提升將近300GHz左右。此一重大技術進展開啟了矽製程在兆赫茲系統應用之序幕，同時對於降低兆赫茲系統成本及面積之可行度大為增加。本論文開發互補式金氧半製程積體電路之設計技術，以基頻振盪模式之鎖相迴路完成次兆赫茲信號源電路設計，期許在未來進一步結合倍頻及天線陣列技術，具體實現高輸出功率且低相位雜訊之兆赫茲信號源，開啟兆赫茲訊號應用之機會。
在傳統高速鎖相迴路信號產生器中，需要串接多級注入式鎖定除頻器將高速輸出頻率降頻至低頻，使其與參考訊號之相位比較，藉由閉迴路之迴授控制達到相位鎖定。然而，操作在100GHz以上之壓控振盪器與注入鎖定除頻器之調頻範圍均極受限制，且對於溫度、製程、及電壓等環境變異十分敏感，容易造成彼此頻率範圍的錯置，進而限制鎖定頻寬甚至無法正確鎖頻。此一問題在兆赫茲頻率範圍之應用將更形嚴峻。
為解決此一難題，本論文提出一個接收機型式之兆赫茲鎖相系統，其利用諧波降頻混波器代替高速注入鎖定除頻器，免除串接多級除頻器的需求，並且提出自動掃頻機制加速鎖頻速度及克服環境變異的問題。本論文一開始將概述兆赫茲信號源之應用背景，且介紹先前文獻所使用的高速鎖相迴路架構，探討其優缺點。而後介紹所提出的接收機形式鎖相迴路架構其操作原理及行為、雜訊模型，並以一個160GHz之晶片實例介紹其詳細子電路架構及整體系統量測結果。最後將總結本論文之成果，並且提出對未來之建議。

關鍵字

鎖相迴路 ； 接收機 ； 接收信號強度指示器 ； 諧波混波器 ； 三倍頻器

並列摘要

In contrast to X-ray, THz wave (300GHz-3THz,T-ray) is a non-ionized light source for non-invasive detection of biological tissues without the concern of much radiation exposure. Thus it is believed as an emerging technology for next generation medical imaging system. Additionally, T-ray is capable to penetrate clothing and many (non-metallic) packaging materials. It opens up unique screening possibilities for detection of concealed weapons, chemicals and biological agents, tumors, cavities, and also opportunities for short range radars and secured high data rate wireless communications.
Until recently, THz range signal sources are mostly addressed by silicon-germanium process or bulky and expensive optics. As the fmax of CMOS reach over 200GHz, it opens up an opportunity to provide a small size and low cost platform in CMOS technology. In this paper, we proposed a CMOS technique to realize a sub-THz signal source, which can be further boosted into THz range with the aid of phase combination or push-push techniques to open up opportunities of THz applications.
To implement a high speed PLL, several cascaded injection-locked frequency divider are used to down convert the high speed output frequency for phase comparison in conventional architecture. For the oscillation frequency close to hundreds of GHz range, the frequency tuning ranges of both VCO and ILFD become very limited, which are highly susceptible to parasitic effects associated with the buffer stage and interconnects. As the injection-locked frequency divider is tend to self-oscillation if it isn’t injection locked properly, the frequency misalignment in divider chain are susceptible to PVT variation and may narrow the locking range of the PLL or cause the loop fail to lock.
To circumvent this critical issue, we propose a novel receiver-based PLL (RX-PLL) for over 100GHz operations. In the proposed RX-PLL, the high speed prescalers are replaced by a harmonic mixer. And with the aid of RSSI for automatically frequency sweeping, the phase-locked loop is capable of fast locking and free of misalignment problems. In this thesis, the background of THz signal source will be introduced, and several architectures for high speed PLL will be discussed. Then we proposed a receiver-based architecture and discuss its behavior and noise model. After that, we accomplished a 160GHz RX-PLL and take it as an example to introduce the detail schematics, and then demonstrate its measurement results. Finally, I will summarize the main results of this thesis. The recommendations for future works are also addressed.

並列關鍵字

Phase-Locked Loop ； Receiver ； RSSI ； Harmonic Mixer ； Tripler

參考文獻

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[3] D. Shim, C. Mao, R. Han, S. Sankaran, E. Seok, C. Cao, W. Knap, and K. K. O, ” Paths to Terahertz CMOS Integrated Circuits”, IEEE 2009 Custom Intergrated Circuits Conference (CICC), pp. 657-663, September, 2009.

[4] Jri Lee, “A 75-GHz PLL in 90-nm CMOS Technology,” ISSCC Dig. Tech. Papers, pp. 432-613, Feb. 2007.

[5] Kun-Hung Tsai and Shen-Iuan Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 276-277, Feb. 2009.

[6] Chung-Yu Wu and Min-Chiao Chen, “A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-μm CMOS for V-Band Applications,” IEEE Transaction on Microwave Theory and Techniques, vol. 57, no. 7, pp. 1629-1636, July 2009.