適用於癲癇偵測之高功率效益生理訊號處理系統晶片之設計與實現

近幾年來，積體電路在現今的個人醫療應用中扮演著重要的角色。這些醫療裝置通常由電池供電，因此，功率消耗的限制帶來訊號擷取及處理的極大挑戰。其中一新興的生醫應用為癲癇發作控制。癲癇為目前常見的神經系統疾病之一，全球約有1%的人患有癲癇。其中，有一大部分的患者無法有效地使用現今的治療方法抑制。可植入式閉迴路神經刺激是一個創新且有效的癲癇抑制方法，而一個即時癲癇發作偵測器是一個閉迴路癲癇控制器的重要核心。在本篇論文中，許多從軟體至硬體層面的低功耗高效能技術被用來做為即時高功率效益癲癇偵測。為展示所提出的構想，三顆晶片被設計實現，並且使用患有自發型失神性癲癇的大鼠為動物模型，以驗證長時間連續的偵測效能。在第一顆晶片中，一個基於32位元精簡指令集架構的生醫訊號處理核心被實現，以達到低功耗且連續即時處理能力。所提出的生醫訊號處理核心包含了5級整數管線、32位元乘法累加器及一個32位元計時器。此核心所擁有的高效能訊號處理及即時排程功能，可用在許多生醫應用上。原本的浮點癲癇偵測演算法被近似成整數運算，且重新排程後以獲得短的計算延遲。此高效能的生醫訊號處理核心被實現在0.18微米互補金屬氧化物半導體製程，以驗證功能及運算能力。根據量測結果顯示，該處理核心與先前基於增強型8051微控制器的雛型系統相比，可降低超過90%的功率消耗。第二顆晶片中，提出一個基於第一顆晶片所設計的高功率效益生理訊號處理器，以用於多樣的生理訊號。在這顆處理器中，內嵌上萬位元組的記憶體以用來有效率的執行程式。多模式類比數位轉換器也被整合至晶片中以擷取生理訊號。為了系統的擴充性，許多串列及並列的介面裝置也被整合至處理器中。藉由指令層集的程式碼優化，大幅改善效能。電壓頻率縮放及時鐘閘控技巧也被應用來降低動態功率消耗。此生醫訊號處理器被實現在0.18微米互補金屬氧化物半導體製程。根據量測結果顯示，該處理核心在即時癲癇偵測模式下，僅消耗百微瓦。此一高度整合、高功率效益的生理訊號處理器可廣泛應用於可攜型醫療裝置。最後一顆晶片中，提出一高功率效益的癲癇偵測系統晶片。一個具有直接記憶體存取的快速傅利葉轉換加速器及亂度編碼加速器被設計，並與第二顆晶片電路整合，提升癲癇偵測運算效能，進而降低動態功率消耗。訊號擷取的緩衝空間及資料控制單元被提出，以減少在訊號擷取時程式切換的時間消耗。此一高功率效益的癲癇偵測系統晶片被實現在0.18微米互補金屬氧化物半導體製程。根據模擬結果顯示，所實現之癲癇偵測系統晶片，在進行即時癲癇偵測情境下，僅消耗數十微瓦。此一極低功耗的系統晶片讓未來植入式閉迴路癲癇抑制可行。結合有效率的硬體架構及軟體優化，該平台的即時處理能力、彈性、可移植性及多樣性及其設計方法不僅可用在閉迴路癲癇控制器，還可應用在許多生醫植入式裝置。

關鍵字

癲癇；癲癇發作偵測；閉迴路；系統晶片；精簡指令集

並列摘要

In recent years, integrated circuits play an important role in today’s personal medical applications. These medical devices are usually battery-powered and their limited power budget imposes design challenges on signal acquisition and processing. Epileptic seizure control is one of the emerging applications. In this application, closed-loop neurostimulation is the most important method for seizure control devices. A real-time seizure detector is the kernel of a closed-loop seizure controller. In this dissertation, several low-power high-performance techniques from software to hardware level are applied for real-time power-efficient seizure detection. To demonstrate the proposed ideas, three works are designed and implemented. Long-Evans rats with spontaneous absence seizures are used as animal models for long-term continuous verification. In the first work, a bio-signal processor (BSP) core based on 32-bit reduced instruction set computer (RISC) architecture for seizure detection is implemented to achieve low-power consumption and continuous real-time processing. The proposed BSP core consists of 5-stage integer pipeline, 32×32 multiply-accumulator (MAC) unit, and a 32-bit tick timer. These features can enable high-performance signal processing and task scheduling for many biomedical applications. The floating-point seizure detection algorithm is approximated and rescheduled for short latency. The high-performance BSP core is implemented in 0.18 m complementary-metal-oxide semiconductor (CMOS) technology to verify functionality and capability. The measurement results show that the implemented processor can reduce over 90% power consumption compared with our previous prototype, which is implemented on an enhanced 8051 microcontroller. In the second work, a power-efficient BSP based on the first work is proposed to utilize for diverse physiological signals. Tens of kilobytes memory is embedded for efficient program execution in the proposed processor. The multi-mode analog-to-digital converter (ADC) is also integrated for physiological signals acquisition. Several serial and parallel ports are integrated with RISC processor for system expansion. Significant performance improvement is achieved through instruction optimization. Voltage and frequency scaling as well as clock gating are applied to reduce dynamic power on this work. The proposed BSP is implemented in 0.18 m CMOS technology. The measurement results show that the BSP consumes hundreds of microwatts to perform real-time seizure detection. The highly integrated and power-efficient BSP can be applied for excessive portable medical devices. The last work presents a power-efficient seizure detection system-on-chip (SoC). The FFT and entropy coding engines with direct memory access (DMA) feature are designed to reduce dynamic power through high-performance computation. The sample buffer and data control unit for signal acquisition is proposed to reduce context switching overhead. The seizure detection SoC is implemented in 0.18 m CMOS technology. The simulation results show that the implemented SoC consumes tens of microwatts to perform real-time seizure detection. The ultra-low power consumption of the proposed SoC enables implantable closed-loop seizure suppression in the future. Combining with efficient hardware architecture and software optimization, the real-time processing capability, design flexibility, portability, and versatility of the proposed platform and its design methodology can be applied on closed-loop seizure controller and many biomedical implants.

並列關鍵字

Epilepsy ； epileptic seizure detection ； closed-loop ； system-on-chip ； RISC

參考文獻

[2] Kilhwan Kim, Unsun Cho, Yunho Jung, and Jaeseok Kim, "Design and implementation of biomedical SoC for implantable cardioverter defibrillators," in Proc. IEEE Asian Solid-State Circuits Conference, pp.248-251, 12-14 Nov. 2007.

[3] Santosh Chede and Kishore Kulat, “Design Overview of Processor Based Implantable Pacemaker,” Journal of Computers, vol. 3, no. 8, pp. 49-57, August 2008.

[4] Sunyoung Kim, Namjun Cho, Seong-Jun Song, Donghyun Kim, Kwanho Kim and Hoi-Jun Yoo, “A 0.9-V 96-μW Digital Hearing Aid Chip with Heterogeneous S-D DAC," Symposium on VLSI Circuits Digest of Technical Papers, pp.55-56, 2006.

[6] Sunyoung Kim, Seung Jin Lee, Namjun Cho, Seong-Jun Song, and Hoi-Jun Yoo, "A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations," IEEE Journal of Solid-State Circuits, vol.43, no.1, pp.266-274, Jan. 2008.

[8] Julius Georgiou, and Christopher Toumazou, "A 126-μW cochlear chip for a totally implantable system," IEEE Journal of Solid-State Circuits, vol.40, no.2, pp. 430- 443, Feb. 2005.

國際替代計量

適用於癲癇偵測之高功率效益生理訊號處理系統晶片之設計與實現

全文下載

主題瀏覽