實現在40奈米製程下可操縱在低電壓的四讀四寫多執行序暫存器叢集設計

隨著攜帶式電子產品，像是手機、筆記型電腦、影像通訊和眾多電腦商品越來越廣泛的運用，一個低功率消耗且可提供SoC晶片平行處理的記憶體是非常重要的課題。在這篇論文中分別探討了兩個主題，第一個是具有二讀二寫8Kb靜態隨機存取記憶體，另一個則是具有四讀四寫2Kb多執行序暫存器叢集設計，兩者皆實現在TSMC 40nm製程上。為了達到高頻寬以及高效能，傳統單一讀寫隨機存取記憶體無法提供夠高的效率，因此我們提出了一顆具有二讀二寫多重埠的靜態隨機存取記憶體，此設計不僅可以解決同時列選取干擾並且可以使用於位元交錯結構，其他設計像是相鄰共用寫入模組、CLK閘控和電壓偵測器阻隔皆可提供節省更多能量消耗。一個8Kb的測試晶片設計與實現在TSMC 40nm製程下，經由電路布局後的模擬顯示，在0.9伏特可操作在475百萬赫茲。另一個設計為具四讀四寫多執行序暫存器叢集設計，新的技術像是一周期兩次寫/讀、支援四個序列並行、資料空位轉移和共用讀取模組。此設計提供廣泛電壓使用，可從0.4伏特到1.2伏特讓使用可以更佳有彈性。考慮低能量消耗技術像是沒有仿造讀取動作、可降低一半讀取電路和字元線保持在高電位。藉由這些設計可大幅降低動態能量消耗以及靜態能量消耗分別為50%和25%。經由電路布局後的模擬顯示在0.9伏特可操作在238百萬赫茲。

關鍵字

靜態隨機存取記憶體；暫存器記憶體叢集

並列摘要

There are wide-ranging usage of portable mobile device (PMD) such as cell phone, notebook and video product and many different types of computers in today markets. It is crucial important to emphasis energy efficiency, low power consumption and parallel memory design in system-on-chips (SoC) recently. In thesis, two topics will be presented. First topic is the low power 2R2W 8Kb multi-port SRAM design, second topic is the low power 4R4W 2Kb multi-thread register file design and implementation in TSMC 40nm CMOS technology. In order to gain high bandwidth and high performance, conventional single-port SRAM design is not efficiency. In this way, we proposed a new structure 2R2W multi-port bit-cell structure, this cell not only eliminate the half select distribute problem but also support bit-interleaving structure. Low power technology such as share WBL structure, CLK gating and SA power gating are included. An 8K test chip is designed and implemented in TSMC 40nm general purpose CMOS process. Post-layout simulation results demonstrate operating frequency of 475 MHz at 0.9V. Another work is 4R4W multi-thread register file design, with double pump, four threads, data slot switch control and share RBL structure technology are proposed. Wide range supply voltage operation form 0.4V to 1.2V, it supply designer has more flexibility. No dummy read operation, reducing RBL to 1/2 and RWL keep VVSS are design for low power consideration. In this work, active power reduction is more than 50% and standby power reduction is less than 25%. Post-layout simulation results demonstrate operating frequency of 238 MHz at 0.9V.

並列關鍵字

SRAM ； Register File

參考文獻

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實現在40奈米製程下可操縱在低電壓的四讀四寫多執行序暫存器叢集設計

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