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  • 學位論文

液晶顯示器之閘極電路改善與模擬

The Gate Circuit Improvement and Simulation of TFT-LCD

指導教授 : 趙昌博

摘要


本論文研究在消費性電子產品追求輕薄短小的趨勢中,TFT-LCD之解析度要求愈來愈高,要在相同尺寸下達到高解析度,所使用的驅動IC數量相對的增加,目前已發展到GIP(Gate Driver In Panel)驅動方式來達到目的,同時達到窄邊框設計(Slim Border)。 GIP即將閘極驅動(Gate Driver)電路設計在玻璃基板上,而在電路設計上,也面臨到a-Si:H TFT材料特性上會發生的應的問題(Stress Effect)。加上所使用TFT Device元件數增多,對TFT Device元件長時間在偏壓與高溫操作下,薄膜電晶體的內部載子引發的缺陷現象,都會導致整片面板失去功能。 本研究藉著參考先進對電路設計進行SPICE建立與模擬,以求利用最少的資源進行電路改善,和減少偏壓效應(Bias Stress Effect)與熱應力(Thermal Stress)的影響,進而達到穩壓效果。

並列摘要


In this paper, Trends in consumer electronics products pursues slim and light, TFT-LCD high resolution requires more and be in the same size to achieve high resolution, the relative increase in the number of drives used in IC, It has been developed to GIP (Gate Driver In Panel) driven approach to achieve their goals, while achieving a narrow frame design (Slim Border). GIP is a gate driver circuit design on a substrate of glass, It’s also facing the a-Si: H Stress Effect on the material properties problems. Coupled with an increase in the number of components used in TFT, the TFT device for a long time under the bias voltage operation, the internal carrier film transistor induced charge trapping defects, cause to display abnormal function of the panel. Reference to others papers and manufacturing process, Use the SPICE simulating to establish a circuit model, in order to use the least resources for circuit improvements and reduce the impact bias stress effect and thermal stress, thus achieving voltage regulation.

並列關鍵字

Gate Driver GIP GIA GOA

參考文獻


[3]Yu-Chung Yang et al.,“Shift Register Circuit” , AU Optronics Corporation, Hsinchu(TW), 2011
[8] Sung Jin Park et al.,“Stability of a-Si:H TFT After High Temperature Annealing”,2006
[9] Z. Tang, M.S. Park, S.H. Jin, C.R. Wie,“Drain bias dependent bias temperature stress instability in a-Si:H TFT”, 2008
[10]Dangling-bond defect in a-Si:H Characterization of network and strain effects by first-principles calculation of the EPR parameters
[12]A. Cerdeira, M. Estrada, B. Iñniguez, J. Pallares, L.F. Marsal, Modeling and parameter extraction procedure for nanocrystalline TFTs, Solid-State Electronics 48 (2004) 103–109

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