低功率低溫多晶矽電晶體之研究

A Study on Low Power Low Temperature Polycrystalline Silicon Transistors

陳昱璇(Yi-Hsuan Chen)

指導教授 ： 趙天生

國立交通大學/理學院/電子物理系所/博士(2015年)

https://doi.org/10.6842/NCTU.2015.00895

摘要

隨著行動電子與穿戴式電子產品的普及，如何降低顯示器上的元件功耗日漸成為一項重要的研究課題。低溫多晶矽(low temperature polycrystalline silicon)薄膜電晶體(thin-film transistor)因為製程溫度低且擁有相當高的場效載子遷移率，有助於提升主動式陣列液晶顯示器(active-matrix liquid-crystal display)中開關元件的電流驅動能力、亮度、開口率與解析度，亦可利用LTPS TFT製作周邊驅動電路與功能性電路並整合至玻璃基板達成系統面板(system on panel)的目標。然而LTPS TFT中因為晶粒邊界隨機散亂分布，因此使得面板上的元件特性均勻性不佳；且在矽晶粒邊界處、多晶矽通道層與閘極介電層接面處存在相當多的缺陷能態密度，導致LTPS TFT相對非晶矽薄膜電晶體具有較高漏電流和較差的均勻度。在本篇論文中，我們分別改變結構或導通機制希望能降低LTPS TFT的功率損耗(power consumption)。
首先，我們提出利用超薄體(ultra-thin body，UTB)結構提升閘極對通道的控制能力以抑制漏電並同時改善次臨界擺幅(subthreshold slope，S.S.)與短通道效應控制能力。在此，我們首度同時探討n型通道與p型通道TFT在通道薄化時電流的不對等變化；當通道厚度由60 nm降低至10 nm時，n型通道TFT的導通電流由358 μA降至25 μA，反觀p型通道TFT的導通電流則由313 μA降至88 μA。我們發現n型通道TFT的導通電流對於通道薄化效應較為敏感，因此在規劃元件佈局時應將該效應納入考量。除此之外，亦發現通道薄化所造成導通電流的劣化可透過閘極氧化層薄化進行補償；以n型通道UTB-TFT為例，當閘極氧化層厚度由20 nm降低為10 nm時，飽和電流可由13 μA增加至25 μA、開關電流比更可提升10.8倍。顯示閘極氧化層薄化後之UTB-TFT在未來低功率操作具有極高的潛力。
接著，我們提出利用相反極性的源極與汲極摻雜方式，以能帶間穿隧(interband tunnel)取代傳統飄移擴散(drift-diffusion)做為新的導通機制，製作出多晶矽穿隧式電晶體(polycrystalline silicon tunnel field-effect transistor，poly-Si TFET)。Poly-Si TFET可望能大幅改善漏電流與次臨界擺幅，然而與傳統單晶矽穿隧式電晶體相比，poly-Si TFET最大差異在於不論在矽晶粒邊界處或多晶矽通道層與閘極介電層接面處皆有許多缺陷存在，因此我們首先利用氮氣電漿鈍化與金屬誘發側向結晶技術探討晶體品質對於poly-Si TFET特性之影響。根據第三章的實驗結果可知氮氣電漿鈍化能有效修補多晶矽通道層與閘極介電層接面處的缺陷，提升導通電流；而金屬誘發側向結晶技術不僅能有效降低多晶矽通道層與閘極介電層接面處的缺陷，同時能放大晶粒尺寸、降低矽晶粒邊界處的缺陷，因此對於poly-Si TFET不論導通電流、S.S.與關閉狀態漏電流皆能有所改善。
此外，我們進一步討論通道層厚度對於poly-Si TFET特性之影響。通道層厚度變薄時，晶粒尺寸隨之變小，將使載子傳輸時受到嚴重的散射作用；然而對於interband tunnel而言，較薄的通道層則有利於加強閘極偏壓對穿隧接面逆向偏壓的調控能力。因此我們利用通道厚度分別為100 nm與50 nm的兩種poly-Si TFET相比較，試探討poly-Si TFET的通道厚度效應。實驗結果發現通道厚度較薄的poly-Si TFET相較通道厚者不僅其關閉狀態漏電流可減少80%、次臨界擺幅可降低181.26 mV/dec，導通電流甚至可提升6倍；顯示通道厚度微縮雖然因缺陷數目增加而可能造成劣化，但其閘極對穿隧能窗(tunnel energy window)控制的增強效果比其劣化程度更為顯著，因此強化閘極對tunnel energy window控制將是poly-Si TFET的重要改善目標之一。
最後，我們綜合上述兩章的研究結果，採用金屬誘發側向結晶技術結合氨電漿鈍化與薄化之閘極氧化層完成通道改良(channel improved)之poly-TFET。該元件相較製作於同一片晶圓上的poly-Si TFT可以展現較陡峭的次臨界擺幅、較低的漏電流以及較緊密的變異性分布。經過氨電漿鈍化處理後，該元件次臨界擺幅僅221 mV/dec，為目前poly-Si TFET文獻中最低紀錄；導通電流達4.65 μA，亦是目前poly-Si TFET文獻中最高紀錄，除此之外poly-Si TFET不論在次臨界區或關閉區相較於poly-Si TFT皆展現較低的變異性，有利應用於大尺寸低功率面板之操作。本篇博士論文中所製作的poly-Si UTB-TFT與poly-Si TFET將在未來低待機功率電路、主動式陣列液晶顯示器驅動元件和三維積體電路運用上皆佔有極高的潛力。

關鍵字

低溫多晶矽 ； 穿隧式電晶體 ； 超薄體 ； 金屬誘發側向結晶

並列摘要

Over recent years, the market demands for portable electronic devices, such as smart phone, tablets, and e-books, continue to grow at a rapid pace. Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in active-matrix liquid crystal displays and active-matrix organic light-emitting diode displays as switching transistors due to high mobility and thus high current drive, high brightness, and high aperture ratio. In addition, poly-Si TFTs have also been developed for versatile applications, including nonvolatile memory, sensors, random-access memory and controller, which makes them potential for achieving system-on-panel application. However, random distribution of grain boundaries in the poly-Si channel may cause variation between devices. Numerous traps located at the grain-boundaries and at the channel / gate oxide interface cause generation current and thermionic field emission current at the off state, which severely deteriorate power consumption and uniformity. In this dissertation, two different low power poly-Si devices are proposed to reduce power consumption via different structure or conducting mechanism.
First, an ultra-thin body (UTB) thin-film transistor with raised source/drain (RS/D) structure is proposed to reduce leakage current, improve subthreshold slope (S.S.), and enhance short-channel effect control at the same time. The UTB effect on both n- and p-type poly-Si TFTs with RS/D structure is studied simultaneously. As channel film thickness is thinned down from 60 nm to 10 nm, the saturation current IDSAT of n-type UTB-TFTs decreases from 358 μA to 25 μA, while that of p-type UTB-TFTs decreases from 313 μA to 88 μA. Because the n-type UTB-TFTs show a relatively severe degradation of IDSAT because of channel film thinning, the layout design for complementary circuits using UTB-TFTs should be more carefully revised. Besides, it is also found that driving current could be substantially improved with scaling of the gate oxide thickness. By decreasing the gate oxide thickness from 20 nm to 10 nm, the IDSAT of UTB-TFTs can be significantly increased from 13 μA to 25 μA, and the on/off current ratio can be magnified by 10.8 times. This results suggest that UTB-TFTs with sub-10 nm gate oxide display a great promise for low power and high performance application in the future.
On the other hand, when the source and drain are doped with opposite type of dopants, the conduction mechanism of drift diffusion can be replaced with interband tunneling. The conventional poly-Si TFT can thus be transformed into poly-Si tunnel field-effect transistor (TFET). As a result, the leakage current and the S.S. may be significantly improved. However, one major difference between poly-Si TFETs and single crystalline silicon TFET is that there are a great amount of defects located either at the grain boundaries or at the channel/gate oxide interface. Therefore, the author would first discuss the impact of crystalline quality on the characteristics of poly-Si TFETs. According to the experimental results in Chapter 3, N2 plasma treatment may effectively passivate the defects at the channel/gate oxide interface, and thus the ON-state current (ION) are considerably improved. Metal-induced lateral crystallization (MILC) technique may not only reduce the density of interface states (Nit) but also enlarge the grain size and reduce the density of grain boundary traps (NGB). For the MILC poly-Si TFETs, both ION, IOFF and S.S. are significantly improved.
Then, the author further investigate the active layer thickness (TCH) dependence of the characteristics of poly-Si TFETs. As active layer thickness decreases, the grain size decreases and the field-effect mobility is degraded due to severe scattering effect. Nevertheless, thinning of active layer favors enhancing gate control over the reverse bias at tunnel junction. In Chapter 4, the active layer thickness effect are discussed via the poly-Si TFET with TCH = 100 nm and 50 nm. The poly-Si TFETs with thinner TCH not only shows a ~ 0.2× lower OFF-state current (IOFF), a significant subthreshold swing reduction (ΔS.S.) ~ 181.26 mV/dec, a ~ 6.20× larger on/off current ratio, but also a 22 % improvement in ION and a ~ 6× enhancement in saturation current (IDSAT). Reducing TCH can significantly enhance the gate control ability over the tunnel energy window at the tunnel junction. Therefore the active layer thickness and the gate oxide thickness shall be thin to improve the performance of poly-Si TFETs.
Finally, on the basis of results in previous chapters, a channel improved poly-Si TFET is proposed with the combination of MILC technique, NH3 plasma treatment, and thinner gate oxide.
This MILC poly-Si TFET with NH3 plasma treatment and thinner gate oxide demonstrate a record low S.S. (~221 mV/dec) and a record high ION (4.65 μA), among the other reported poly-Si TFETs, and a high on/off ratio > 106 at VDS= 1 V. Besides, the poly-Si TFETs show a much smaller variation at either OFF-state or subthreshold region compared with the poly-Si TFTs, which is beneficial for the low power application on larger scale panels. In conclusions, The UTB-TFTs and poly-Si TFETs proposed in this study display a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays (AMLCD), and three-dimensional integrated circuits applications in the future.

並列關鍵字

LTPS ； TFET ； UTB ； MILC

參考文獻

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