考量半導體製程能力限制下之晶圓圖隨機性辨識法及應用

半導體產業是一種高投資產業，每間公司在製程上所投資的成本都很高。由於半導體產業製程相當複雜，因此，對每間公司而言，如何使製程穩定與良率提升便是一個很重要的目標。晶圓圖是半導體產業中偵測製程異常的重要參考依據。當非隨機性的異常晶圓圖發生時，常代表製造過程發生異常。藉由這些異常晶圓圖的圖形，也可幫助工程師找出可能發生的原因，例如機台發生問題或哪個製程步驟有異常等。對於分辨隨機與非隨機晶圓圖的議題已有很多相關研究，分別提出一些可以取代人工目視判斷方式的方法，以減少由於人為主觀的因素所導致的圖形判斷結果不一致。然而在半導體廠製造技術水準與機台能力或產品特性等限制下，常導致晶圓圖上某些區域容易產生故障品，此種原因所形成的異常晶圓圖形並非是特殊的製程異常所引起，而是基於半導體廠製造技術水準與機台能力或產品特性的根本限制。此種「異常」和真正有歸屬原因的「異常」，一般電腦自動辨識方法是分不出來的。在本篇論文中，在分辨晶圓圖形是否隨機，我們針對此種製程能力的限制提出一個修正方法，期能正確判定真正的晶圓圖異常。此方法將可協助工程師快速掌握製程異常的發生並加以排除，使製程穩定並提升良率。

關鍵字

已知良好裸晶；空間隨機性檢定；半導體產業；基本能力；晶圓圖

並列摘要

The semiconductor industry is a very competitive and high-investment industry. The manufacturing process is one of the areas that are heavily invested. Semiconductor manufacturing are so complex that improving the process stability and yield is essential for each company to stay competitive. The wafer sort map (WSM) is a useful tool for detecting abnormal processes. Non-random patterns on a WSM usually provides clues about process problems. With particular patterns, WSMs can help engineers to identify possible causes, such as problems in equipments or process steps. Some automatic methods were proposed to distinguish between random and non-random WSMs in the literature, attempting to replace the labor-intensive human recognition operations for cost saving as well as to reduce the inconsistency due to subjective human judgements. In practice, however, almost all WSMs exhibit some regions of inherent failures, which generally are due to process limitations caused by, say, layouts, equipments, process technologies, etc. This kind of failures are inevitable at the present technology level; thus, in the view of statistical process control, they should be considered as caused by common causes instead of process problems caused by special causes. Thus, in fab, such failures are often accepted and referred to as the aseline" of the process. Unfortunately, without accounting for, the baseline, most of the existing automatic methods will classify these baseline patterns as non-random patterns. In this thesis, we propose a new approach to detecting WSMs with "genuine" nonrandom WSM by taking the baseline into account. Three eective schemes are developed and studied. Eective detection of patterned WSMs can help engineers to trace process failures of particular patterns back to their root causes and then improve the process stability and yield by eliminating these causes.

並列關鍵字

known good die ； spatial randomness test ； semiconductor industry ； baseline ； wafer sort map

參考文獻

[1] S. P. Cunningham and S. McKinnon, Statistical Methods for Visual Defect Metrol-

ogy," IEEE Transactions on Semiconductor Manufacturing, vol. 11, no. 1, pp. 48-53,

[2] C. K. Hansen and P. Thyregod, Use of Wafer Maps in Integrated Circuit Manufac-

turing," Microelectronics Reliability, vol. 38, pp. 1155-1164, 1998.

Integrated Circuit Fabrication Processes for Spatially Clustered Defects," Techno-

國際替代計量

考量半導體製程能力限制下之晶圓圖隨機性辨識法及應用

全文下載

主題瀏覽