二位元分離式閘極氮化矽快閃式記憶體之漏電機制探討

The Investigation of Charge Loss Mechanism in Dual-Bit Split-Gate SONOS Flash Memory

何永涵(Yung-Hang Ho)

指導教授 ： 莊紹勳

國立交通大學/電機學院/電子工程系所/碩士(2010年)

https://doi.org/10.6842/NCTU.2010.00740

摘要

利用缺陷捕抓電荷之記憶體元件對於其尺寸之微縮是很有利的。在本篇論文中，我們提出一種二位元分離式閘極氮化矽快閃式記憶體。在最佳化之電壓操作下，利用源極注入(SSI)之寫入以及帶對帶電洞入射(BTBHH)抹除，相較於傳統式氮化矽快閃式記憶體，此種快閃式記憶體可以達成較高寫入速度、低功率消耗以及低位元間之干擾，然而保留著傳統式氮化矽快閃式記憶體之特性。

資料漏失是氮化矽快閃式記憶體最為重要之可靠度議題。水平向與垂直方向之電荷漏失機制已被提出且爭論，因為對於傳統式氮化矽快閃式記憶體，水平方向和垂直方向之電荷漏失幾乎不可能分離出來。在此論文中，我們提出了對分離式閘極氮化矽快閃式記憶體減少電荷流失的方法。藉由改變分離式閘極氮化矽快閃式記憶體之上閘極之長度或在抹除操作時之隱藏閘極施加一小電壓，水平方向和垂直方向之電荷漏失即可被分離出來。我們可以觀察到，水平方向之資料漏失是由於電子和電洞間之分佈差異所導致，且最長之上閘極元件之電荷流失是最短上閘極元件之電荷流失的兩倍。

最後，我們提出一種基底瞬時熱電洞射入之抹除方式可以完整的消除儲存的電子並且造成低電子電洞之差異分佈，而導致低橫向資料流失。因為橫向之資料流失被抑制，此時可以觀察到資料流失與上閘極長度是無相關的並且可以防止電壓區間在10年的生存期間縮小對於二位元分離式閘極氮化矽快閃式記憶體。

關鍵字

氮化矽快閃記憶體 ； 分離閘 ； 源極入射 ； 資料漏失

並列摘要

Devices based on charge trapping are a promising solution for flash memory scaling. In this study, a dual-bit split-gate SONOS flash memory has been proposed. Under the optimized bias operation, the split-gate structure device by utilizing source-side injection (SSI) programming and band-to-band hot hole injection (BTBHHI) erasing can achieve high program speed, low power consumption and low interference caused by the other bit while preserving the same performance of the conventional NROM device.

The charge loss in nitride based charge trapping memory has been a major reliability issue. The charge loss mechanisms have been published and uncertain whether the leakage path is along the lateral or vertical direction, since it is impossible to separate the two directions loss for conventional structure. In this paper, a new approach to reduce the charge loss in a split-gate SONOS memory has been proposed. By altering the word-gate length of the split-gate structure SONOS or by applying a small bias at the control-gate under erasing, the electron or hole distribution can be varied, and the lateral and vertical retention loss can be split off. It was observed that the lateral retention loss is caused by the misalignment between the distribution of electron and hole. The retention loss of the longest word-gate device is about two times larger than the shortest device ones caused by lateral retention loss.

Finally, substrate transient hot hole (STHH) injection erasing scheme has been demonstrated to fully eliminate the electrons throughout the entire channel and achieve low electron and hole misalignment, inducing low lateral data retention loss. Since the lateral retention loss has been suppressed, the retention loss is independent of the word-gate length with time and avoids window closure for the 10-year lifetime after the program/erase cycling in split-gate structure SONOS cells.

並列關鍵字

SONOS ； split-gate ； source-side injection ； data retention loss

參考文獻

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