氟摻雜對應變矽於二氧化鉿堆疊式金氧半場效電晶體其特性和可靠度的影響

根據2007年ITRS所訂定出的金氧半場效電晶體的閘極尺寸，當元件尺寸持續縮小，因傳統的二氧化矽介電層，當厚度降到1至1.5奈米左右，會有顯著的量子穿隧效應而導致漏電流大到無法忍受的規範。近年來使用高介電質材料來取代二氧化矽介電層已被廣泛研究。相較於二氧化矽，在相同的等效厚度(EOT)之下，高介電質物質有較厚的實際厚度,因此可以抵擋因量子穿遂效應而導致的大量漏電。然而，以高介電質材料當閘極介電層卻遭遇到其它的問題要解決，如：介面的粗糙度導致載子遷移率的下降；高介電質材料有較高的界面狀態產生及較多的電荷捕捉，對臨限電壓的漂移有較嚴重的影響。研究指出，材料間的應變作用，可讓遷移率上升，故驅動電流會有大幅度的提升，對現今微縮的COMS元件來說，用應變作用導致遷移率上升，是非常重要的突破，因為它不用增加額外的製程步驟卻可以提供更高的驅動電流，如:淺塹渠絕緣(shallow trench isolation，STI)，矽化反應(slicidation)，接觸孔蝕刻停止層(contact etch stop layer，CESL)等製程，皆可運用存在其應力施加於通道，使遷移率上升。其中，接觸孔蝕刻停止層是最普遍使用於nMOSFET的方式。然而，以電漿增強型化學氣相沉積(PECVD)沉積出的Si3N4氮化物薄膜，理想比並不佳，其薄膜化學式更準確地可寫成SixNyHz，指出它為非理想比組成且其薄膜含有氫(通常為9至30%)。其氫離子在後續製程中，會向下擴散至通道，使表面有大量的Si-H鍵，這種較弱的鍵結，容易被熱載子打斷，造成元件在做熱載子應力的穩定性不佳和可靠度劣化的問題。本文提出在閘極介電層沉積前，使用離子佈值的方式使氟離子在後續的高溫摻雜活化的過程中，使其擴散至通道和閘極介電層。我們發現，摻雜氟對於應變矽元件的基本特性沒有顯著的降低，而分析可靠度方面，我們深入探討固定電壓應力(CVS)和熱載子應力(HCS)效應下的影響。觀察到在應力的破壞下，有氟摻雜的元件，有較小的臨界電壓偏移，對於元件的可靠度和穩定性都有明顯的改善。其主要原因是來自於氟原子併入高介電閘極主體以及閘極層與通道界面間，不僅可修補界面狀態的懸空鍵結(interface dangling bond)和較低界面狀態產生，且可有效減少高介電閘極本體的捕捉電荷情形。最後在應力測試後再進行回復(relaxation)的行為，在CVS下的回復行為，觀察載子具有逃逸(de-trapping)特性，而有氟摻雜的元件有較少載子捕捉情形(應力下)及較高逃逸能障使得有較少逃逸現象產生(回復下)，這與先前討論Frenkel-Poole傳導機制，有較深的載子捕捉位置有好的關連性。

關鍵字

高介電質；應變矽；氟

並列摘要

From the scaling trend in ITRS 2007, the conventional SiO2 layer, which is only 1-1.5 nm thickness, would suffer serious leakage from tunneling effect. Therefore, the High-K dielectric layer is used to replace SiO2 dielectric layer. We could apply its predominance to avoid its serious tunneling leakage current from quantum tunneling effect under the same effective oxide thickness (EOT), because the High-K dielectric has thicker physical thickness. However, this replacement also faces some challenges to solve. Like, degraded channel mobility from interface roughness; more serious VTH shift from higher interface states generations and more oxide bulk charges, etc. As our known, we could enhance mobility for drive current by strain engineering. In fact, for nowadays scaling CMOS, it is essential for better mobility. It is a good technique to improve driving current without extra processes. The techniques like, shallow trench isolation (STI), slicidation, contact etch stop layer (CESL) all could insert strain into channel for better mobility. Most of all, the most widely used technology is CESL for nMOSFETs. However, it could face the setbacks from its uncontrollable quality Si3N4 deposited by PECVD. Since its variable composition control, the layer is called SixNyHz precisely, which indicates its hydrogen content (9~30%). Worst of all, hydrogen would diffuse into the interface of dielectric layer and channel and then eventually result degraded reliability and uncontrollable characteristics。 In my thesis, we incorporate fluorine before gate dielectric deposition via channel implantation technique, which was subsequently diffused into the gate stack during annealing process. The implanted fluoride effect little for device characteristics degradation. For its reliability, we also analyze deeply its effect on constant voltage stress (CVS) and hot carrier stress (HCS). We found the device with fluoride dopants would suffer smaller VTH shift after stress. It is on of evidences fluoride advantage on its reliability and stability improvement. The predominance mainly comes from dopanted fluorine ions into the interface between interface of dielectric layer and channel would recovery interface dangling bonds result in lower interface state generations and eventually reduces High-K dielectric layer bulk trapping. After CVS relaxation, with fluorinated device,less carrier are trapped after stress and less de-trapping from deeper traps barrier height after relax. This phenomenon could elucidate from Frenkel-Poole emission for relation between de-trapping and its traps location.

並列關鍵字

high-k ； strain silicon ； fluorine

參考文獻

Chapter 1

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[3] A. Hori and B. Mizuno, “CMOS device technology toward 50nm region performance and drain architecture”, IEDM Tech. Dig., p.641, 1999.

[6] C-Y. Hu, D. L. Kencke, and S. Banerjee, “Determining effective dielectric thickness of MOS structures in accumulation mode”, Appl. Phys. Lett., 66 (13), p.1638 ,1995.

[8] J. H. Stathis, “Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits”, IEEE Transactions on Device and Materials Reliability, Vol. 1, pp. 43 -59, 2001.

國際替代計量

氟摻雜對應變矽於二氧化鉿堆疊式金氧半場效電晶體其特性和可靠度的影響

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