利用覆晶技術與單石微波積體電路製作之Ka/V頻段放大器

Design and fabrication of Ka/V-band amplifiers by flip-chip and MMIC technologies

李啟賢(Chi-Hsien Lee)

指導教授 ： 辛裕明

國立中央大學/資訊電機學院/電機工程學系/碩士(2006年)

摘要

本論文分別設計兩種不同技術的V頻段與Ka頻段放大器，分別為單石微波放大器(MMIC Amplifier)，與利用覆晶(Flip-Chip)技術在氧化鋁基板上製作覆晶式微波放大器(MIC Amplifier)。第一部份所設計的V頻段單石微波放大器乃利用穩懋半導體公司(WIN)0.15 um pHEMT製程技術來實現。在被動元件上的設計係採用共平面波導傳輸線(CPW)來進行電路之匹配、偏壓電路設計。二級放大器設計方法是將第二級利用負載推移(Load-Pull)的模擬對負載阻抗做匹配，使其提供最大的輸出功率(Pout)；第一級的電路匹配則採用共軛匹配(Conjugate Match)的方式，提供較大的增益(Gain)。在小訊號特性表現方面其中心頻率為62.8 GHz，S11、S22與S21分別為-2.59 dB、-16.40 dB與13.33 dB。
第二部份介紹覆晶技術在高頻電路的應用，首先，先建立覆晶凸塊模型，再利用覆晶技術製作Ka頻段放大器。在高頻電路的應用上，由於頻段愈高而波長愈短，以往的鎊線(Wire Bonding)在高頻操作時所產生寄生效應會影響整體電路的特性表現，故已不再適用。然而，先完成覆晶模型的建立，再應用於電路上，是非常重要的步驟。在Ka頻段放大器中，主動元件採用穩懋半導體公司(WIN)0.15 um pHEMT製程所提供的元件；在被動元件方面，主要是利用共平面波導傳輸線易於設計的優點並配合苯並環丁烯(BCB)，製作於氧化鋁基板上。在小訊號特性表現方面其中心頻率為38 GHz，與模擬值相差6 GHz，而主要原因可能是被動元件製程、RF pads模型和覆晶凸塊(Flip-Chip Bump)模型與實際電路特性有些微誤差所造成。小訊號參數S11、S22、S21分別為-5.56 dB、-5.87 dB、10.49 dB；在功率特性方面，其線性增益為10.59 dB而增益壓縮1 dB點之輸出功率為17.53 dBm、PAE為10.27 %。若微調RF pads模型，最後的模擬結果與量測結果就相當一致了。藉由覆晶式電路的實現，證明所製作出的被動元件與覆晶技術是可以成功地應用在高頻電路上；且於文獻中利用覆晶技術(Flip-Chip Assembly)製作放大器，在這方面的發表並不是非常廣泛，故我們所製作出來的電路與衍生出來的問題都是日後要設計高頻電路的重要依據。

關鍵字

單石微波積體電路 ； 放大器 ； 覆晶技術

並列摘要

In this thesis, two different microwave amplifiers were designed by using monolithic microwave integrated circuit (MMIC) and flip-chip technology for V- and Ka-band applications, respectively.
A V-band MMIC amplifier was realized by WIN 0.15 um pHEMT process. The passive components including matching networks and bias circuits were designed and fabricated by coplanar waveguide (CPW) topology. The design method of two-stage amplifier utilized load-pull simulation to find maximal output power (Pout) for output matching network at second stage and adopted complex conjugate matching to derive sufficient gain for input matching network at first stage. The operating frequency was at 62.8 GHz with scattering parameter S11, S22 and S21 of -2.59 dB, -16.40 dB and 13.33 dB, respectively.
Secondly, a microwave integrated circuit using flip-chip technology for Ka-band is presented. In the application of the microwave circuit, the wire bonding connection could produce serious parasitic effect in high frequency. Therefore, it is important to use flip-chip bonding. At first, flip-chip bump model was developed, and then Ka-band amplifier by using flip-chip technology was designed and fabricated. The active device (0.15 um pHEMT) was fabricated by WIN semiconductor, and the passive components were mainly utilized by CPW to integrate with BCB and fabricated on the alumina substrate. The operating frequency was simulated at 38 GHz, but the measured results show a 6 GHz difference. The possible reasons may result from the variation from the passive component process, RF pads model and flip-chip bump model. The measured small signal parameters S11, S22 and S21 were -5.56 dB, -5.87 dB and 10.49 dB, respectively. In the power performance, the linear gain was 10.59 dB, output power at 1 dB compression point was 17.53 dBm and PAE was 10.27 %. If RF pads model parameters are tuned, it showed good agreement between simulation and measurement. By the realization of the presented Ka-band flip-chip assembly pHEMT circuit, it is possible that the passive components made on separate substrates and flip-chip technology could apply successfully to the high frequency circuits.

並列關鍵字

amplifier ； MMIC ； flip-chip

參考文獻

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