類神經網路應用於高階電流模型之研究

High-Level Current Macro Model using Neural Network

楊侑承(Yu-Cheng Yang)

指導教授 ： 劉建男

國立中央大學/資訊電機學院/電機工程學系/碩士(2006年)

摘要

再現今這個單晶片(System on Chip)系統設計的時代，為了要縮短設計的時 間，以及增加單晶片的可靠度與效能，便希望能在設計的初期就能夠知道每一個 區塊的電流資訊，如此就能及早作功率的最佳化，也能儘早考慮到SSN (simultaneous switch noise) 和IR-drop 這類雜訊的影響。此外對於電源線的設計 與佈局，也有很大的幫助。因此高階的電流模型在單晶片設計上便有舉足輕重的 地位，而且在使用上不需要知道內部電路的資訊，就可以很快速的得到電路區 塊的電流波形，也使得在應用上非常方便，對於IP 智慧財產權的保護，更是有 幫助。 因此本篇論文提出了一個利用類神經網路來建立的高階電流模型，並利用 HSPICE 做部分波形的模擬，再利用階級化的技巧來簡化電路中電流波形和輸入 輸出轉態情況的關係，並合併同一級的輸入輸出來降低類神經網路的複雜度，就 可以利用類神經網路學習不同的輸入向量與其相對應電流波形之間的關係，利用 論文中提出的方法流程，可以針對不同的CMOS 數位組合電路建構個別的電流 模型，且在模型建好之後，能夠同時對不同形狀的電流波形做估計，可說是非常 方便有效率。

關鍵字

高階電流模型 ； 類神經網路

並列摘要

Nowadays, the era of system on chip design, we hope to know about the current
information of the logic block for shorting the design cycle and improving the
reliability and performance of the chips. Therefore we can optimize the power and
consider about the noise influence, such like SSN, IR-Drop, as soon as possible. And
the current information also help for the design of power line and layout. So the high
level current model plays an important role of the system on chip design. We do not
need to know the detail information for drawing the current waveform of the logic
block. And the IP protection is the advantage of the high level model.
In this thesis, we propose a high level current model constructed by neural
network. We got parts of current waveforms by HSPICE simulation. And use the
levelize technique to simplify the relationship of waveform and the input output
transition status. Merge the same level input and output can reduce the complexity of
the neural network. Follow the flow which we proposed, the model will be
constructed. We can use this model to estimate current waveforms which have
different shapes. It is very convenient use and efficient computation.

並列關鍵字

high level current model ； neural network

參考文獻

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[2] Yi-Min Jiang; Krstic, A.; Kwang-Ting Cheng, ” Estimation for maximum

instantaneous current through supply lines for CMOS circuits”, Very Large Scale

current and delay evaluation,” IEEE Trans. Computer-Aided Design, vol. 13, pp.

[4] A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, “A modeling technique for