地面與手持數位電視廣播同步迴路之設計與實現及低功率技術

低功率設計一直是晶片設計的重要課題，尤其是愈來愈普及的可攜式電子裝置之使用時間受限於電池的有限載荷量。手持式數位電視廣播(DVB-H)利用時間切割技術來降低移動式接收機之功率消耗。在本論文中，我們著重於暫存器轉換層次的低功率設計技術之討論。我們的團隊分別針對架構和系統的低功率和低晶片面積觀點來設計此DVB-T/H基頻內接收機。我們採用一些低功率及功率察覺(power-aware)的設計以降低我們的DVB-T/H基頻內接收機的功率消耗。這些技術包含有預先計算、時脈閘控、運算元隔離、差值編碼、硬體共享、記憶體之分時多工讀寫、低功率算術運算架構以及功率管理者。最後，我們使用標準單元設計流程來實現此基頻內接收機。此基頻內接收機的架構包含有快速富利葉轉換(FFT)、前處理器(差分器、反旋轉器、彈性緩衝區、相位累加器)、後處理器(粗略符碼同步、散佈領航碼同步、通道估測)、快速富利葉轉換後估測(整數載波頻率誤差估測、餘數載波頻率誤差/取樣時脈誤差估測)。針對快速富利葉轉換後估測的部份(亦即同步迴路)，我們降低了51.6 %的晶片面積以及53.3 %的功率消耗。此外，我們所提出的功率管理者依照不同的保護區間長度，降低系統在誤差追蹤模式3% ~ 20%之功率消耗。

關鍵字

低功率技術；同步迴路；數位電視廣播

並列摘要

Low power design is still an important issue of IC design; in particular, the popularizing portable electronic devices are time-limited used because of the finite energy capacity of battery. Digital Video Broadcasting for Handheld (DVB-H) introduces the time-slicing technique to decrease the power consumption of mobile receiver. In this thesis, we focus on the discussion about the register transfer level (RTL) low power design techniques. And our team designs the DVB-T/H baseband inner receiver with the low power and low area consideration in respect of architecture and system level. We utilize several low power and power aware design techniques to reduce the power consumption of our DVB-T/H baseband inner receiver. These techniques include pre-computation, clock gating, operand isolation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture and power manager. At last, we use the cell based design flow to implement our baseband inner receiver. The architecture of baseband inner receiver consists of FFT, Pre-processor (Interpolator, Derotator, elastic buffer and phase accumulator), Post-processor (Coarse Symbol Synchronization, Scattered Pilot Synchronization and Channel Estimation) and Post-FFT estimation (ICFO estimation and RCFO/SCO estimation). For the Post-FFT estimation (that is, synchronization loop), the area is reduced 51.6% and the power consumption is reduced 53.3%. Moreover, the proposed power manager reduces 3% ~ 20% power consumption according to different Guard Interval (GI) when the system is operating during the offset tracking mode.

並列關鍵字

Low Power Technique ； Synchronization Loop ； Digital Video Broadcasting

參考文獻

[1] ETSI, “Digital Video Broadcasting: Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television,” European Telecommunication Standard EN 300 744 V1.5, Nov. 2004

[4] R. S. Guindi, and F. N. Najm, “Design techniques for gate-leakage reduction in CMOS circuits,” International Symp. Proc. Quality Electronic Design, Mar. 2003, pp. 61 – 65.

[7] M. Pedram, J. M. Rabaey, Power Aware Design Methodologies, Kluwer Academic, 2002.

[9] K. K. Parhi, VLSI Digital Signal Processing Systems, WILEY INTERSCIENCE.

[11] D. R. Smith, P. Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall, 2000.

國際替代計量

地面與手持數位電視廣播同步迴路之設計與實現及低功率技術

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